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Non-overlapping signal circuit and system with adjustable width

A signal circuit, non-overlapping technology, applied in the field of microelectronics, can solve the problems that the delay accuracy cannot be controlled arbitrarily, the switching control timing delay value is large, the size of the switch tube is large, etc., to achieve strong scalability, reduce chip area, The effect of simplifying complexity

Active Publication Date: 2019-04-26
SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For example, in high-power power management chip switch control circuits, the size of the internal switch tube itself is very large, and the delay value of the switch control timing is sometimes very large. If you use a traditional circuit, you want to obtain a delay of microseconds or even milliseconds. The circuit is obviously not suitable. Even if the conditions are met, a lot of capacitors and resistors are required. The sacrifice of area directly leads to an increase in cost, and the delay accuracy cannot be controlled arbitrarily.

Method used

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  • Non-overlapping signal circuit and system with adjustable width
  • Non-overlapping signal circuit and system with adjustable width
  • Non-overlapping signal circuit and system with adjustable width

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Embodiment Construction

[0025] According to the attached Figure 2-6 , give a preferred embodiment of the present invention, and give a detailed description, so that the functions and characteristics of the present invention can be better understood.

[0026] see figure 2 , a non-overlapping signal circuit with adjustable width of the present invention, comprising: a main control signal input terminal 1, a first inverter 2, two signal output circuits 31, 32, a delay logic unit 4 and four signal Output terminals 51, 52, 53, 54, signal output terminals 51, 52, 53, 54 are arranged in pairs on the two signal output circuits 31, 32 correspondingly, wherein the output terminal of the first inverter 2 is connected to the first signal output In the circuit 31 , the main control signal input terminal 1 is respectively connected to the input terminal of the first inverter 2 and the second signal output circuit 32 , and the delay logic unit 4 is connected to the two signal output circuits 31 and 32 .

[0027...

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Abstract

The invention provides a width-adjustable non-overlapping signal circuit and system. The width-adjustable non-overlapping signal circuit comprises a main control signal input end, a first phase inverter, two signal output circuits, a delay logic unit and an even number of signal output ends; each signal output circuit comprises a NAND gate and a phase inverter group which are connected in series and in sequence; the first input end of the NAND gate of the first signal output circuit is connected with the output end of the phase inverter group of the second signal output circuit; and the first input end of the NAND gate of the second signal output circuit is connected with the output end of the phase inverter group of the first signal output circuit. The width-adjustable non-overlapping signal circuit and system can realize non-overlapping signals with an adjustable width range, and internal integration of a capacitance and external connection of a capacitive load are unnecessary; and the width-adjustable non-overlapping signal circuit and system have the advantages of being simple in structure, small in volume, simple to control, easy in implementation and multi-channel integration and low in development cost.

Description

technical field [0001] The invention relates to the technical field of microelectronics, in particular to a non-overlapping signal circuit and system with adjustable width. Background technique [0002] With the rapid development of integrated circuits, the level of integration is getting higher and higher, and the miniaturization and low cost of chips are the development trend of chips. see figure 1 A traditional non-overlapping signal circuit, using the delay loop formed by the first inverter 2, the NAND gate 301 and the second inverter 302, the delay generated is very limited. For example, in high-power power management chip switch control circuits, the size of the internal switch tube itself is very large, and the delay value of the switch control timing is sometimes very large. If you use a traditional circuit, you want to obtain a delay of microseconds or even milliseconds. The circuit is obviously not suitable. Even if the conditions are met, a lot of capacitors and...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K19/08
CPCH03K19/08
Inventor 汪明亮覃荣华解永生周磊磊唐洪莹刘建坡
Owner SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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