Embedded chip testing method and system

Abstract

The invention discloses an embedded chip testing method and system, which comprises a tester, a testing platform and a latch, wherein the tester is suitable for generating a test signal and outputting the test signal through a test signal output end; the testing platform comprises a test signal input end, a latch control end and a test result output end, wherein the test signal input end is independently coupled with the test signal input end of the tester and the test signal input end of an embedded chip, and the latch control end is coupled with the latch; the test result output end is coupled with the test result input end of the tester; and the latch comprises a response signal input end and a latching data output end, wherein the response signal input end is coupled with the data output end of the embedded chip, and the latching data output end is coupled with the test result output end. By use of the method and the system, the test time delay of the embedded chip can be reduced, and test speed is improved.

Description

technical field [0001] The invention relates to the field of chip testing, in particular to an embedded chip testing method and system. Background technique [0002] Embedded memory IP has no external pins, which can save pad (PAD) space and the space occupied by pins, so it is widely used in system-on-chip (SOC). [0003] In practical applications, before the embedded memory leaves the factory, the function of the embedded memory can be tested to know whether the current embedded memory can work normally. Since the embedded memory has no pins but only electrode contacts, it cannot be tested directly by existing chip testing devices. [0004] In the prior art, built-in self-test (Built In Self Test, BIST) is usually used to indirectly test the embedded memory, and the embedded memory is connected to the test device through a probe card and connecting wires, so as to test the embedded memory. memory for testing. [0005] However, when the existing BIST method is used to te...

AI Technical Summary

Problems solved by technology

[0005] However, when using the existing BIST method to test the embedded memory, there is a delay in the input and output ports of the test device, and there is a problem of long test delay, which makes it impossible to perform high-speed frequency testing

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