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Time shifter and method thereof

A shifter and timing technology, applied in pulse processing, electrical components, logic circuits, etc.

Active Publication Date: 2016-12-28
REALTEK SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

figure 1 A timing shifter 100 is shown, including a first buffer 100P and a second buffer 100N, the composition of the timing signal X includes two logic signals X + with X － , at this time the timing signal X' consists of two logic signals X' + with X' － , since a buffer holds the value of a signal but causes a delay, therefore, in addition to the delay caused by the first buffer 100P, the X' + is equivalent to X + ; Similarly, except for the delay caused by the second buffer 100N, the X' － is equivalent to X －

Method used

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Embodiment Construction

[0076] Exemplary embodiments of the inventive concept relate to a timing shifter. Although this specification mentions several examples of the present invention, which relate to the preferred mode of implementing the inventive concept, the inventive concept can be implemented in many ways, that is, the inventive concept is not limited to the specific embodiments described below. An implementation example or a specific mode, wherein the specific implementation example or mode contains implemented technical features. Furthermore, well-known details are not shown or described in order to avoid obscuring the presentation of characteristics of the inventive concept.

[0077] The inventive concept is disclosed from an engineering point of view, wherein if the difference between a first quantity and a second quantity is less than a given tolerance range, the first quantity can be said to be is "equal to" the second magnitude. For example, if the given tolerance range is 0.5mv or ot...

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Abstract

The invention discloses a timing shifter, which includes: a first gating buffer, used to receive a first logic signal and output a second logic signal; a second gating buffer, used to receive a a third logic signal and a delay signal; and a finite state machine for receiving the delay signal and a clock signal, wherein the first gating buffer is used to be conditionally enabled according to the state of the finite state machine , and the second gated buffer is enabled regardless of the state of the finite state machine.

Description

technical field [0001] The apparatus and method of the present invention and exemplary embodiments thereof relate to temporal signal processing. Background technique [0002] Those skilled in the art can understand terms and basic concepts in the field of microelectronics in this disclosure, such as voltage, signal, circuit, logic signal, clock, trip point, inversion Inverter, buffer, circuit node, finite state machine, data flip-flop, multiplexer, MOS (metal oxide semiconductor), PMOS (p-channel metal oxide semiconductor), NMOS (n-channel metal oxide semiconductor), CMOS ( Complementary metal oxide semiconductor), transistors, source, gate, drain, and CMOS inverters. Such terms and basic concepts are obvious to those skilled in the art, so relevant details will not be repeated here. [0003] In this disclosure, a logic signal refers to a signal with two states, the two states are "high" and "low", which can also be said to be "1" and "0". For the sake of brevity, when a ...

Claims

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Application Information

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IPC IPC(8): H03K5/13
CPCH03K5/159H03K19/0948H03K2005/00058H03K5/13
Inventor 林嘉亮
Owner REALTEK SEMICON CORP