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A positioning method for the abnormal resistance value of the via chain structure of a semiconductor chip

A positioning method and technology of via chain, which is applied in single semiconductor device testing, semiconductor/solid-state device testing/measurement, resistance/reactance/impedance measurement, etc. It can solve the problems of low positioning accuracy and inability to locate through holes, etc.

Active Publication Date: 2019-09-27
WUHAN XINXIN SEMICON MFG CO LTD
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  • Abstract
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Problems solved by technology

[0008] However, the above-mentioned method for locating via holes with abnormal resistance values ​​in the via chain structure is difficult to capture through the low-light microscope (EMMI) or light-induced resistance change (OBIRCH) mode for samples with a small increase in resistance value (<5 times). Hot spots (hotspots), and thus cannot locate the failed vias, and this method has low positioning accuracy

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  • A positioning method for the abnormal resistance value of the via chain structure of a semiconductor chip
  • A positioning method for the abnormal resistance value of the via chain structure of a semiconductor chip

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Embodiment Construction

[0032] In the following description, a lot of specific details are given in order to provide a more thorough understanding of the present invention. Of course, in addition to these detailed descriptions, the present invention can also have other embodiments.

[0033] Aiming at the failure situation where the resistance value of the through-hole chain structure is not greatly increased, the present invention proposes a method for locating the through-hole with abnormal resistance value in the through-hole chain structure, which is simple, easy to operate and accurate.

[0034] The present invention will be further described below with reference to the drawings and specific embodiments. Obviously, the described examples are only a part of the examples of the present invention, but not all examples. Based on the examples summarized in the present invention, all examples obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the p...

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Abstract

The present invention relates to the field of semiconductors, in particular to a method for locating the abnormal resistance value of a through-hole chain structure of a semiconductor chip. The through-hole chain at the predetermined position is defined as the chain to be tested, and the metal at both ends of the chain to be tested is exposed. line; test the resistance between the metal wires at both ends of the via chain to obtain the first test resistance value; define a predetermined number of equal-length test segments on the chain to be tested, and expose two of each of the test segments The metal wire at the end; test the second test resistance value between the metal wires at both ends of each test section, and determine the through hole with abnormal resistance value according to the first test resistance value and the second test resistance value In the test section, the method of the present invention is a method for locating abnormal through-holes in the case of a failure in which the resistance value increases little in the through-hole chain structure. The method is simple, easy to operate and accurate in positioning.

Description

Technical field [0001] The invention relates to the field of semiconductors, and in particular to a method for locating abnormal resistance value of a through-hole chain structure of a semiconductor chip. Background technique [0002] With the continuous improvement of product quality requirements, the failure analysis of semiconductor chips has attracted more and more attention. Failure analysis is a system that studies the characteristics and laws of product failure phenomena, analyzes the causes of failure, and proposes corresponding countermeasures in reliability engineering. Analysis method. In a semiconductor chip with a through-hole chain structure, the method of locating the failure point in the through-hole chain structure through failure analysis is as follows: [0003] The first is to expose the metal wire on the upper layer of the via by grinding the target area, and then locate the failure point by voltage contrast in a scanning electron microscope (SEM). [0004] Scann...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/66G01R31/26G01R27/02
Inventor 李辉谢渊仝金雨
Owner WUHAN XINXIN SEMICON MFG CO LTD