Unlock instant, AI-driven research and patent intelligence for your innovation.

Chip security testing method and system based on fault injection

A technology of fault injection and safety testing, which is applied in the detection of faulty computer hardware, error detection/correction, instruments, etc. It can solve the problems that high-precision fault injection testing cannot be performed, and achieve the effect of improving accuracy and accuracy

Active Publication Date: 2022-02-01
SHENZHEN INST OF ADVANCED TECH
View PDF0 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] The embodiment of the present invention provides a chip security testing method based on fault injection to solve the technical problem in the prior art that high-precision fault injection testing cannot be performed when the semiconductor manufacturing process develops from micron to deep submicron or even nanometer nodes

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Chip security testing method and system based on fault injection
  • Chip security testing method and system based on fault injection
  • Chip security testing method and system based on fault injection

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0025] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with the embodiments and accompanying drawings. Here, the exemplary embodiments and descriptions of the present invention are used to explain the present invention, but not to limit the present invention.

[0026] In an embodiment of the present invention, a chip security testing method based on fault injection is provided, such as figure 1 As shown, the method includes:

[0027] Step 101: Using the synchronous control unit to focus the femtosecond laser on different positions on the surface of the chip to be tested in sequence, and perform fault injection on different positions of the chip to be tested, wherein the femtosecond laser is in the chip to be tested Two-photon absorption occurs, so that the logic unit in the chip under test is flipped;

[0028] Step 102: When the chip to be tested is...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The embodiment of the present invention provides a chip security testing method and system based on fault injection, wherein the method includes: sequentially focusing the femtosecond laser on different positions on the surface of the chip to be tested through a synchronous control unit, and different parts of the chip to be tested Fault injection is performed at the position, wherein the femtosecond laser produces two-photon absorption in the chip to be tested, so that the logic unit in the chip to be tested is flipped; when the chip to be tested is irradiated by the femtosecond laser to different positions, Collecting the operation results output by the chip to be tested respectively; comparing and analyzing the collected operation results with the preset correct operation results of the chip to be tested, and determining whether an effective fault occurs at the position where the chip to be tested is irradiated by the femtosecond laser, The number of positions where effective faults occur is the basis for judging the safety degree of the chip under test. This solution can improve the accuracy of fault injection, and is beneficial to improve the success rate of chip security testing based on fault injection.

Description

technical field [0001] The invention relates to the technical field of chip testing, in particular to a chip security testing method and system based on fault injection. Background technique [0002] With the development of space technology and nuclear technology, semiconductor ionizing radiation effects (also known as single event effects) are further classified and studied, such as single event latch-up (Single event latch-up, SEL for short), single event upset (Single event upset, SEU for short), single event functional interrupt (Single event functional interrupt, SEFI for short), and single event burnout (Single event burnout, SEB for short), etc. According to whether the impact of single event effects on electronic components can be recovered, single event effects can be divided into unrecoverable errors and recoverable errors. "Non-recoverable error" or "hard error" refers to an error that will cause fatal and permanent damage to the device or system once it occurs, ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/22
CPCG06F11/2268
Inventor 邵翠萍李慧云唐烨
Owner SHENZHEN INST OF ADVANCED TECH