level shift circuit

Abstract

The invention provides a level shifting circuit. The level shifting circuit comprises a Schmitt trigger, an amplitude limit circuit and an anti-phase circuit, wherein an input signal of a voltage signal input end is received by the Schmitt trigger, a square wave signal is sent by the Schmitt trigger to the amplitude limit circuit, the square wave signal after amplitude limit is sent by the amplitude limit circuit to the anti-phase circuit, the signal outputted by the anti-phase circuit and the input signal have same phases, the Schmitt trigger comprises a transmission high voltage module, a transmission low voltage module and an overturning circuit, an input end of the transmission high voltage module and an input end of the transmission low voltage module are respectively electrically connected with the voltage signal input end, a high voltage signal is sent by an output end of the transmission high voltage module to the overturning circuit, a low voltage signal is sent by an output end of the transmission low voltage module to the overturning circuit, and a square wave signal is outputted by the overturning circuit according to the high voltage signal and the low voltage signal. The level shifting circuit is advantaged in that a relatively good duty ratio and relatively good anti-jitter and anti-burring capabilities can be further acquired while high pressure resistance is realized.

Description

technical field [0001] The invention relates to the field of level shifting circuits, in particular to a level shifting circuit capable of withstanding high voltage. Background technique [0002] With the rapid development of integrated circuit technology, it has now entered the level of 28nm and other deep sub-micron. Under such an advanced technology, the working voltage of the device is getting lower and lower, and the voltage that the device can withstand is getting lower and lower. For example, under such an advanced process, the voltage VDD that the device can withstand is 1.8V, and an excessively high voltage will damage or even destroy the device. However, the voltage of many interface signals may still maintain a voltage of 3.3V or higher. Therefore, under the condition that the voltage VDD that the device can withstand is 1.8V, when the designed circuit needs to work at a voltage of 3.3V or 2VDD, it is necessary to consider the problem of device withstand voltage ...

AI Technical Summary

Problems solved by technology

[0003] However, the disadvantages of the prior art are as follows: 1. When the rising and falling edges of the input signal with an amplitude of 2VDD are very slow, it will cause relatively large duty ratio distortion

Because when the input signal passes through the native NMOS tube, the voltage part higher than the amplitude of 1VDD is cut off, and the remaining part of 1VDD will cause a large duty cycle distortion when passing through the Schmitt trigger U1. figure 1 The voltage waveforms output by each node in the figure 2 shown

2. The ability of anti-shake and glitch is limited

Because the threshold point and hysteresis window of the Schmitt trigger U1 are not enough compared to 2VDD, it is easy to cause signal glitches or the ability to suppress glitches is not strong enough, such as image 3 As shown, when the input signal Vin1 generates jitter or burr, and the amplitude of jitter or burr is larger than the hysteresis window of Schmitt trigger U1, the output level signal of Schmitt trigger U1 will also have jitter or burr. This will affect the performance of the level shifting circuit to some extent

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