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FinFET (Fin Field-Effect Transistor) split gate structure complementary symmetric logic-based Inclusive OR-exclusive OR circuit

A complementary and symmetrical technology, applied in the same-or-exclusive-or circuit field, can solve problems such as insufficient drive capability, large number of FinFET tubes, large circuit power consumption and time delay, etc., to reduce layout area and power consumption, and reduce leakage current Effects of power consumption, power reduction, and latency

Active Publication Date: 2017-02-08
NINGBO UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The same-or-exclusive-or circuit based on the static complementary logic of the same gate structure of FinFET devices uses complementary symmetrical logic to generate an exclusive-or signal, and then the inverter generates a same-or signal. Although this circuit has no static power consumption and high level quality, it requires FinFET The large number of tubes will inevitably increase the layout area. At the same time, since the input signal of the same-or-exclusive-or circuit has four (A, B, is the inversion signal of A, is the inversion signal of B), the input signal ( and ) is obtained by converting the input signal (A and B) by additionally equipped with a FinFET tube that forms an inverter function, which will inevitably increase the key jump node, resulting in an increase in the power consumption and delay of the XOR circuit. Leakage current consumes a lot of power
The same-or-exclusive-or circuit based on the transmission gate logic of the same gate structure of the FinFET device uses the transmission gate logic to realize the exclusive-or signal and then generates the same-or signal through the inverter. Although the transmission tube logic will not cause the threshold loss of the output level, it uses The large number of FinFET tubes will also increase the layout area, and the input signals of the same-or-exclusive-or circuit also have four (A, B, is the inversion signal of A, is the inversion signal of B), the input signal ( and ) is obtained by converting the input signals (A and B) through an additional FinFET tube that forms an inverter function. Therefore, the power consumption and time delay of the same-or-exclusive-or circuit are also large, and the leakage current consumes a lot of power, and , the input signal of the same-or-exclusive-or circuit is connected through the source of the transmission gate, which will result in insufficient drive capability when outputting the same-or-exclusive-or signal

Method used

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  • FinFET (Fin Field-Effect Transistor) split gate structure complementary symmetric logic-based Inclusive OR-exclusive OR circuit
  • FinFET (Fin Field-Effect Transistor) split gate structure complementary symmetric logic-based Inclusive OR-exclusive OR circuit
  • FinFET (Fin Field-Effect Transistor) split gate structure complementary symmetric logic-based Inclusive OR-exclusive OR circuit

Examples

Experimental program
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Embodiment 1

[0016] Embodiment one: if image 3As shown, a NOR and XOR circuit based on FinFET divided-gate structure complementary symmetric logic, including a first FinFET tube M1, a second FinFET tube M2, a third FinFET tube M3, a fourth FinFET tube M4, and a fifth FinFET tube M5 , the sixth FinFET tube M6, the seventh FinFET tube M7 and the eighth FinFET tube M8, the first FinFET tube M1, the third FinFET tube M3, the fourth FinFET tube M4 and the seventh FinFET tube M7 are P-type FinFET tubes, the second The FinFET tube M2, the fifth FinFET tube M5, the sixth FinFET tube M6 and the eighth FinFET tube M8 are N-type FinFET tubes, the number of fins of the first FinFET tube M1 and the sixth FinFET tube M6 is 3, and the number of fins of the second FinFET tube M2, the third FinFET tube M3, the fourth FinFET tube M4, the fifth FinFET tube M5, the seventh FinFET tube M7 and the eighth FinFET tube M8 have 1 fin; the source of the first FinFET tube M1, the third The source of the FinFET M3 a...

Embodiment 2

[0017] Embodiment two: if image 3 As shown, a NOR and XOR circuit based on FinFET divided-gate structure complementary symmetric logic, including a first FinFET tube M1, a second FinFET tube M2, a third FinFET tube M3, a fourth FinFET tube M4, and a fifth FinFET tube M5 , the sixth FinFET tube M6, the seventh FinFET tube M7 and the eighth FinFET tube M8, the first FinFET tube M1, the third FinFET tube M3, the fourth FinFET tube M4 and the seventh FinFET tube M7 are P-type FinFET tubes, the second The FinFET tube M2, the fifth FinFET tube M5, the sixth FinFET tube M6 and the eighth FinFET tube M8 are N-type FinFET tubes, the number of fins of the first FinFET tube M1 and the sixth FinFET tube M6 is 3, and the number of fins of the second FinFET tube M2, the third FinFET tube M3, the fourth FinFET tube M4, the fifth FinFET tube M5, the seventh FinFET tube M7 and the eighth FinFET tube M8 have 1 fin; the source of the first FinFET tube M1, the third The source of the FinFET M3 ...

Embodiment 3

[0019] Embodiment three: as image 3 As shown, a NOR and XOR circuit based on FinFET divided-gate structure complementary symmetric logic, including a first FinFET tube M1, a second FinFET tube M2, a third FinFET tube M3, a fourth FinFET tube M4, and a fifth FinFET tube M5 , the sixth FinFET tube M6, the seventh FinFET tube M7 and the eighth FinFET tube M8, the first FinFET tube M1, the third FinFET tube M3, the fourth FinFET tube M4 and the seventh FinFET tube M7 are P-type FinFET tubes, the second The FinFET tube M2, the fifth FinFET tube M5, the sixth FinFET tube M6 and the eighth FinFET tube M8 are N-type FinFET tubes, the number of fins of the first FinFET tube M1 and the sixth FinFET tube M6 is 3, and the number of fins of the second FinFET tube M2, the third FinFET tube M3, the fourth FinFET tube M4, the fifth FinFET tube M5, the seventh FinFET tube M7 and the eighth FinFET tube M8 have 1 fin; the source of the first FinFET tube M1, the third The source of the FinFET M...

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Abstract

The invention discloses a FinFET (Fin Field-Effect Transistor) split gate structure complementary symmetric logic-based Inclusive OR-exclusive OR circuit. The Inclusive OR-exclusive OR circuit includes a first FinFET, a second FinFET, a third FinFET, a fourth FinFET, a fifth FinFET, a sixth FinFET, a seventh FinFET and an eighth FinFET; the first FinFET, the third FinFET, the fourth FinFET and the seventh FinFET are P-type FinFETs; the second FinFET, the fifth FinFET, the sixth FinFET and the eighth FinFET are N-type FinFETs; each of the first FinFET and the sixth FinFET is provided with three fins; and each of the second FinFET, the third FinFET, the fourth FinFET, the fifth FinFET, the seventh FinFET and the eighth FinFET is provided with one fin. Under a condition that performance of the circuit is not affected, the area, power consumption and delay of the circuit are small, and the driving ability of the circuit is strong.

Description

technical field [0001] The present invention relates to an XOR circuit, in particular to an XOR circuit based on complementary symmetrical logic of a FinFET split-gate structure. Background technique [0002] With the ever-increasing application demands, the speed and power consumption requirements of digital electronic systems continue to increase. As a basic unit in a digital electronic system, a full adder can not only complete addition, but also participate in operations such as subtraction, multiplication, and division. It is widely used in large-scale integrated circuit design. The performance of the full adder is good or bad The effect on the performance of digital electronic systems is particularly important. The same-or-exclusive-or circuit is a basic logic unit. It has been widely used in the design of the full adder. As one of the important components of the full-adder, it improves the speed of the same-or-exclusive-or circuit and reduces the speed of the same-or...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K19/21H03K19/20
CPCH03K19/20H03K19/215
Inventor 胡建平许仲池
Owner NINGBO UNIV
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