Transistors and methods of forming them

Abstract

A transistor and its forming method. The transistor includes: providing a substrate including a first region and a second region; forming a dielectric layer on the surface of the substrate, with a first opening in the dielectric layer in the first region, and a dielectric layer in the second region There is a second opening; a gate dielectric layer is formed on the surface of the dielectric layer, the sidewall and bottom surface of the first opening, and the sidewall and bottom surface of the second opening; a covering layer is formed on the surface of the gate dielectric layer, and the material of the covering layer is the first A type of work function material; a first work function layer is formed on the surface of the covering layer in the first region, and the material of the first work function layer is the first type of work function material; the covering layer on the surface of the first work function layer and the second region A second work function layer is formed on the surface, and the material of the second work function layer is a second type work function material; a gate layer filling the first opening and the second opening is formed on the surface of the second work function layer. The mismatch problem between PMOS transistors and NMOS transistors is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a transistor and a forming method thereof. Background technique [0002] Static Random Access Memory (SRAM), as a member of memory, has the advantages of high speed, low power consumption and compatibility with standard processes, and is widely used in computers, personal communications, consumer electronics (smart cards, digital cameras, Multimedia player) and other fields. [0003] The storage unit of the SRAM includes a 4T (transistor) structure and a 6T (transistor) structure. For a 6T SRAM size unit, it includes: a first PMOS transistor P1 , a second PMOS transistor P2 , a first NMOS transistor N1 , a second NMOS transistor N2 , a third NMOS transistor N3 and a fourth NMOS transistor N4 . Wherein, the P1 and P2 are pull-up transistors; the N1 and N2 are pull-down transistors; and the N3 and N4 are transfer transistors. [0004] In the prior art, in ord...

AI Technical Summary

Problems solved by technology

[0006] However, due to the difference in work function layer materials required for PMOS transistors and NMOS transistors, the performance of the formed SRAM is unstable.

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