A method of erasing NAND Flash

Abstract

The invention discloses a Nand Flash erasing method. The method comprises the following steps: step 101, carrying out soft erasing operation on an erase block; step 102, examining whether memory units in the erase block satisfy the erasing conditions or not; step 103, if the memory units in the erase block satisfy the erasing conditions, stopping the erasing operation, and if the memory units in the erase block do not satisfy the erasing conditions, executing step 104; and step 104, lifting the current erasing voltage applied on the erase block according to a preset step value, carrying out erasing operation on the erase block, and returning to the step 102. The provided erasing method can reduce the charge traps in Nand Flash memory units during the erasing process, reduces the threshold voltage shift of memory units, and thus relieves the erasing degradation of Nand Flash, so the number of erasing is increased, and the service life is prolonged.

Description

technical field [0001] The invention relates to the technical field of storage device hardware, in particular to a method for erasing a Nand Flash. Background technique [0002] Nand Flash is a kind of Flash memory, which is a non-volatile memory device (Non-volatile Memory Device). It uses a non-linear macro-cell mode inside, which has the advantages of large capacity and fast rewriting speed, and is suitable for the storage of large amounts of data. figure 1 It is a simple structural diagram of Nand Flash in the prior art, which is composed of a memory cell array 11, a word line selection unit 12, a bit line selection unit 13, a voltage pump 14, and a control unit 15 of the entire Nand Flash chip, wherein the memory cell The array 11 includes memory cells arranged based on word lines and bit lines of each memory cell. Specifically, the memory cells are firstly connected by word lines and bit lines to form a page, then a plurality of pages are formed into a block, and fina...

AI Technical Summary

Problems solved by technology

The change of the threshold voltage of the floating gate 203 of the memory cell can affect the state change of the memory cell. It should be noted that the erasing and programming operations are opposite. In the existing erasing or programming operation method, one erasing or programming process applies Erase pulses or program pulses are constant

Based on the existing programming and erasing methods, some electrons do not have enough energy to reach the floating gate 203 during the process of tunneling to the floating gate during the programming operation, but are trapped in the tunnel oxide layer 24. During the erasing operation The electrons trapped in the tunnel oxide layer 24 cannot migrate from the tunnel oxide layer 24 to the P-type semiconductor substrate 23 after being erased by high voltage.

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