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Data reading and writing method of FIFO (First Input First Output) data cache and data cache thereof

A technology of data buffer and data buffer area, which is applied in the electronic field and can solve the problem that FIFO data buffer cannot realize M-in and N-out data reading methods, etc.

Active Publication Date: 2017-03-15
HISENSE VISUAL TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Embodiments of the present invention provide a data reading and writing method of a FIFO data buffer and a data buffer, which solves the problem that the existing FIFO data buffer cannot realize the data reading mode of M in and N out

Method used

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  • Data reading and writing method of FIFO (First Input First Output) data cache and data cache thereof
  • Data reading and writing method of FIFO (First Input First Output) data cache and data cache thereof
  • Data reading and writing method of FIFO (First Input First Output) data cache and data cache thereof

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Embodiment Construction

[0026] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0027] Some of the terms involved in this application are explained below for the convenience of readers:

[0028] "The data bit width of the FIFO data buffer", that is, THE WIDTH often seen in English materials, it refers to the data bits of a read and write operation of the FIFO data buffer, just like MCU (English: Microcontroller Uni, Chinese: Micro control unit) has 8 bits and 16 bits, ARM32 bits, etc. The width of the FIFO is fixed in the single-chip fini...

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Abstract

The embodiment of the invention provides a data reading and writing method of an FIFO (First Input First Output) data cache and the data cache, relates to the field of computers and solves the problem that the existing FIFO data cache cannot achieve an M-input and N-output data reading manner. The data reading and writing method of the FIFO data cache comprises the following steps: obtaining first to-be-written data with data bit-width of M-bit when the FIFO data cache is in a writing state, caching the first to-be-written data in a data caching area of the FIFO data cache, splitting the first to-be-written data into M 1-bit data blocks, and successively storing the M 1-bit data blocks in first M storage units of the FIFO data cache. The data reading and writing method is applied to the FIFO data cache.

Description

technical field [0001] The invention relates to the field of electronic technology, in particular to a data reading and writing method of a first-in-first-out FIFO data buffer and the data buffer. Background technique [0002] At present, in the current ASIC (English: Application Specific Integrated Circuit, Chinese: Application Specific Integrated Circuit) design, it is usually done by setting an appropriate number of FIFO (English: First Input First Output, Chinese: First In First Out) data buffers. Data caching, to prevent data loss or handle data failures. The FIFO data buffer is a first-in first-out data buffer, and the data that enters first is read out from the FIFO data buffer first. Specifically, the existing FIFO data buffer includes a plurality of storage units, and the data bit width stored in each storage unit is equal and is the smallest unit of the FIFO data buffer. Therefore, the existing FIFO data buffer is performing data writing When entering and reading...

Claims

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Application Information

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IPC IPC(8): G06F12/0855G06F5/06
CPCG06F5/06G06F12/0855
Inventor 郑磊杨青黄修珉
Owner HISENSE VISUAL TECH CO LTD
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