Intra-cluster memory line-column two-stage switching circuit in array processor

Abstract

An intra-cluster memory line-column two-stage switching circuit is mainly applicable to an array structure including an array processor PEG consisting of4*4 light kernel processing units PE at an upper layer and 4*4RAM blocks with the size of 512*16 bit and used for completing interaction access between the array processor and high-speed data among distributed memories and belongs to the technical field of integrated circuit design. The circuit adopts a 'line exchange + column exchange' two-stage switching structure, strategies are preferentially accessed through the line-column two-stage switching structure and a local storage unit, and parallel complete access of the 4*4 array processor to 16distributed storage blocks can be completed, the priority strategy that local storage is prior to remote storage is supported, data access delay is decreased, access bandwidth can be increased, and the resource utilization rate can be improved.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit design, and in particular relates to data parallel access of a distributed storage structure in a 4*4 array processor cluster in an array processor. Background technique [0002] With the increase in the number of computing cores inside the processor, the integrated functions are becoming increasingly complex, and the demand for data access to the main memory is also gradually increasing. Serious, and become an important factor restricting the improvement of processor performance. In order to achieve a balance between processing speed and storage speed, the mainstream storage structure uses multi-level Cache technology to alleviate the worsening "storage wall" problem. However, the multi-level Cache structure requires additional circuits to complete address mapping and ensure data consistency. With the continuous advancement of integrated circuit technology, the number of processor co...

AI Technical Summary

Problems solved by technology

With the continuous advancement of integrated circuit technology, the number of processor cores integrated on the chip has increased significantly, and additional circuits will also increase accordingly. Using a multi-level Cache storage structure will not only increase the complexity of the circuit, but also consume more energy.

Compared with processors using multi-level Cache technology, the existing non-Cache structure faces the problems of insufficient memory access bandwidth, high access complexity, and poor processor memory access flexibility.

To this end, the storage structure in the array processor cluster is studied to improve the parallelism of the memory access process, and on this basis to alleviate the "storage wall" problem between the processor and the memory, and to solve the increase in additional circuits brought about by multi-level Cache technology , complex storage architecture, and poor memory access flexibility of processors have become increasingly urgent

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