83 results about "Interchange circuit" patented technology

A memory device includes at least one swap circuit swapping a plurality of decoded row addresses with one repair address using repair data, at least one register storing the repair data, a wordline activation signal driver receiving the repair address and outputting a wordline activation signal, and a sub-wordline driver activating corresponding sub-wordlines in response to the wordline activation signal.

The invention belongs to the technical field of FFT (Fast Fourier Transform) calculation acceleration, and particularly relates to a self-adaptive FFT operation processor module for processing large data volume, which comprises an address generation module, a data rearrangement unit, a twiddle factor storage module, an FFT calculation module and a control module, the FFT calculation module comprises m rows of radix-2kMDC modules which are arranged side by side; the data rearrangement unit comprises a read-write data storage module and a data preprocessing module; the read-write data storage module consists of a plurality of memories; the data preprocessing module is composed of a plurality of parallel branch switching circuits and a plurality of shuffling units with different depths; the twiddle factor storage module is used for storing fixed constant twiddle factors and realizing repeated utilization of the constant twiddle factors according to the calculated points; the address generation module is used for generating an address sequence for data reading / writing by using a program counter, the control module is used for controlling and executing FFT calculation, and different FFT calculation requirements can be met. And the utilization rate of the butterfly operation unit and the calculation throughput rate of the whole architecture are improved.

The present disclosure relates to a power routing circuit (200) having first and second input nodes (VIN1, VIN2) for connection to respective first and second power supplies and an output node (VOUT1) for connection to a load. The power routing circuit (200) comprises a first main switching circuit (200) connected between the first input node (VIN1) and the output node (VOUT1) and configured to conductively connect the first input node (VIN1) to the output node (VOUT1) if a voltage at the first input node (VIN1) is higher than a voltage at the output node (VOUT1), and a first auxiliary switching circuit (240) connected between the second input node (VIN2) and the output node (VOUT1) and configured to conductively connect the second input node (VIN2) to the output node (VOUT1) if a voltage at the second input node (VIN2) is higher than the voltage at the output node (VOUT1) and the voltage at the first input node (VIN1) is at least a threshold amount lower than the voltage at the second input node (VIN2).

A networking device and networking method for use in industrial automation applications. The networking device includes redundant circuitry that can allow the networking device to continue normal operation in the event of a failure that occurs with hardware of the networking device. The networking device includes both primary and secondary network switch circuits, and associated components. The networking device can be an advanced physical layer (APL) switch that interfaces with APL field devices.

A semiconductor circuit includes a first pad, a second pad, swapping circuit, and an internal circuit. The internal circuit receives a first external signal and a second external signal, and generates a first internal signal and a second internal signal. Based on master information and swapping information, the swapping circuit couples the internal circuit to one of first and second pads to provide a path through which the first internal signal is output and a path through which the first external signal is received, and couples the internal circuit to the other of the first and second pads to provide a path through which the second internal signal is output and a path through which the second external signal is received.

A repeater device as switch node in a wireless communication system, includes a donor antenna that obtains a first beam of RF signals from an upstream neighboring node. The repeater device further includes a switch circuit that detects a label in a preamble of each data frame of a plurality of data frames carried by first beam of RF signals independent of decoding other header information and user data in each data frame and determines routing decisions for the plurality of data frames based on the detected label in each data frame. The plurality of data frames is then switched, via a RF switching fabric, based on the detected label in each data frame such that each data frame is routed to a corresponding service phased antenna array of the plurality of service phased antenna arrays for communication via a plurality of service phased antennas.

A first layer one link aggregation master comprises a first port coupled to receive customer traffic; a first channel; a second channel; an aggregation engine coupled to the first and second channels; a first switch circuit coupled to the first port and to the first channel, and configured to communicate the customer traffic from the first port over the first channel to the aggregation engine, the aggregation engine including a splitter circuit configured to use layer one information to segment at least a portion of the customer traffic into a first virtual container and a second virtual container, the aggregation engine further including an encapsulation circuit configured to encapsulate the second virtual container using Ethernet standards for transport over the second channel; a radio access card configured to generate an air frame based on the first virtual container for wireless transmission over a first wireless link of a link aggregation group to the receiver; and a second switch circuit coupled to the second channel, and configured to communicate the Ethernet-encapsulated second virtual container over an Ethernet cable to a slave for wireless transmission over a second wireless link of the link aggregation group to the receiver.

A semiconductor die defect detection device including a current mirror providing a first current on its first output and a second current on its second output, the first and second currents being identical, a swap circuit having a first terminal connected to the first output of the current mirror, a second terminal connected to the second output of the current mirror, a third terminal and a fourth terminal. The device also includes a die ring circuitry disposed at edges of the semiconductor die including a first plurality of segments disposed on a first leg of the die ring circuitry, and a second plurality of segments disposed on a second leg of the die ring circuitry. The device further includes a voltage comparator including a positive input terminal, a negative input terminal and an output terminal, and an adjustable resistor.

The present disclosure provides a double ring path setting method and apparatus that can improve learning efficiency by reducing the size of data to be transmitted for each path and reducing communication bottlenecks caused by mutual collective communication between multiple computation nodes by using an edge switching circuit that connects between edge nodes connected to edge computation nodes of a computation array composed of multiple computation nodes in a two-dimensional mesh topology, thereby setting two bidirectional ring paths passing through all computation nodes.

An integrated circuit includes a central region having first multiplexer circuits and first busses that interconnect the first multiplexer circuits. The integrated circuit also includes a network-on-chip. The network-on-chip includes switch circuits, second multiplexer circuits, second busses that interconnect the switch circuits, third busses that interconnect the switch circuits and the second multiplexer circuits, and fourth busses that interconnect the first multiplexer circuits and the second multiplexer circuits. Each of the second multiplexer circuits is coupled to at least two of the switch circuits through a subset of the third busses.

A repeater device as switch node in a wireless communication system, includes a donor antenna that obtains a first beam of RF signals from an upstream neighboring node. The repeater device further includes a switch circuit that detects a label in a preamble of each data frame of a plurality of data frames carried by first beam of RF signals independent of decoding header information and user data in each data frame. The plurality of data frames is then switched, via an RF switching fabric, based on the detected label in each data frame such that each data frame is routed to a corresponding service phased antenna array of the plurality of service phased antenna arrays for communication via a plurality of service phased antennas. The switch circuit further generates control signals corresponding to the switched plurality of data frames and transmit the control signals to the RF switching fabric.

A system includes a system-on-chip containing a variety of agents configured to generate data transactions, a communication network configured to transfer transactions between two or more of the agents, a variety of network switches, and a bandwidth control circuit. The network switching circuits can be coupled to the agents and to the network. One of the network switches can be configured to estimate the bandwidth requirements for transactions to be sent through the network switch in an upcoming window.The bandwidth control circuit can be configured to limit network power consumption by determining a bandwidth budget using a network power budget for the upcoming time window and by generating a global bandwidth forecast using estimated bandwidth requirements received from the network switches. The bandwidth control circuit can also be configured to allocate the bandwidth budget among the network switches using the global bandwidth forecast.

The invention provides a tensor data exchange circuit and a data stream processing device and method.The tensor data exchange circuit is used for a data stream processor and comprises a first non-blocking full-arrangement assembly and a second non-blocking full-arrangement assembly; performing data format conversion of in-block data exchange and inter-block data exchange on a plurality of sub-data blocks split by input data through the first non-blocking full-arrangement component and the second non-blocking full-arrangement component so as to output data meeting the format requirement of a target component; wherein the first non-blocking full-arrangement component is used for carrying out in-block data exchange on the sub-data blocks; and the second non-blocking full-arrangement component performs inter-block data exchange on the plurality of sub-data blocks.

The present invention relates to an energy storage device (MCLk) comprising an energy storage element (CLk) supplying a voltage (Vclk) and a main switching circuit (COMk) forming an H-bridge the states of which are selectively controllable, the energy storage element (CLk) being able to deliver to connection terminals, in a first state, the voltage (Vclk), in a second state, the voltage inverted and, in a third state, a zero voltage configuring the storage device (MCLk) into a bypass state, bypassing the storage element (CLk), and further comprising a secondary bypass circuit (CCk) for bypassing the main switching circuit (COMk) electrically connected to the first and second connection terminals (S1, S2), able to configure a redundant fourth state bypassing the main switching circuit (COMk).

The utility model discloses a radio station voice switching system, comprising at least one short-wave radio station which receives and sends far-end voice data through an HF wireless channel; the at least one ultra-short wave radio station is used for receiving and sending far-end voice data through a VHF (very high frequency) or UHF (ultra high frequency) wireless channel; the network voice switching device comprises a network switching board, a switching board and a power supply module, the switching board is connected with the network switching board through a connector, the network switching board comprises an MCU core module, a serial port circuit and a switching circuit, and the network switching board is used for processing and forwarding voice data. The short-wave radio station and the ultra-short-wave radio station are both in communication connection with the network voice switching device. The radio station voice switching system provided by the utility model can realize automatic switching and control of voice services between a short-wave radio station and an ultra-short-wave radio station, and improves communication efficiency and flexibility.

An apparatus includes a system-on-chip that includes a plurality of agents configured to generate data transactions, a communication network configured to transfer transactions between two or more of the agents, a plurality of network switches, and a bandwidth regulation circuit. The network switching circuits may be coupled to the agents and to the network. One of the network switches may be configured to estimate a bandwidth need for transactions to be sent via the network switch in an upcoming window. The bandwidth regulation circuit may be configured to moderate power consumption of the network by determining a bandwidth budget using a network power budget for the upcoming time window, and determining a global bandwidth forecast using estimated bandwidth needs received from the network switches. The bandwidth regulation circuit may also be configured to allocate, using the global bandwidth forecast, the bandwidth budget among the network switches.

An apparatus and method for reducing the memory bandwidth of executing machine learning models. A computing system includes two or more processing nodes, each including at least one or more processors and a corresponding local memory. Switch circuitry communicates with at least the local memories and a system memory of the computing system. The switch includes multiple direct memory access (DMA) interfaces. Each of one or more processing nodes stores multiple embedding rows of embedding tables. A processor of the processing node identifies two or more embedding rows as source operands of a reduction operation. The switch executes memory access requests to retrieve data of the two or more embedding rows from the corresponding local memory, and generates a result by performing the reduction operation. The switch sends the result to the local memory.

An apparatus includes a system on chip including a plurality of agents configured to generate data transactions, a communication network configured to pass transactions between two or more of the agents, a plurality of network switches, and a bandwidth adjustment circuit. The network switching circuitry may be coupled to a proxy and to a network. One of the network switches may be configured to estimate bandwidth requirements for transactions to be communicated via the network switch in an upcoming window. The bandwidth adjustment circuitry may be configured to regulate power consumption of the network by determining a bandwidth budget using a network power budget for an upcoming time window and determining a global bandwidth prediction using an estimated bandwidth demand received from the network switch. The bandwidth adjustment circuitry may also be configured to allocate a bandwidth budget among the network switches using the global bandwidth prediction.

The analog-to-digital converter includes a switching circuit, a first capacitor array, a second capacitor array, and a comparator. The method for operating the analog-to-digital converter includes, during a first sampling period, switching a switching signal to a first level to cause the switching circuit to couple the first capacitor array to a first input terminal of the comparator and a first signal source, and to couple the second capacitor array to a second input terminal of the comparator and a second signal source, and during a second sampling period, switching the switching signal to a second level to cause the switching circuit to couple the first capacitor array to the second input terminal of the comparator and the second signal source, and to couple the second capacitor array to the first input terminal of the comparator and the first signal source. The control logic circuit switches the switching signal between the first level and the second level in a uniform order during a plurality of sampling periods.

The application discloses a kind of non-transparent bridge PCIe exchange circuit dynamic burn-in device and method, adopt root complex CPU, endpoint device, port mode configuration line, port interconnection bus and device state indication line, cover the physical layer of circuit, data link layer and transaction layer and non-transparent bridge address conversion and exchange function, so that circuit is carried out dynamic burn-in according to normal working frequency and bus interface rate during burn-in;The application does not need to be externally connected root complex CPU and numerous PCIe endpoint devices for each non-transparent bridge PCIe exchange circuit, and only one root complex CPU is needed on the whole burn-in board, the connection mode of root complex CPU greatly saves the cost of components on burn-in board;The application improves the density of burn-in device on the same area burn-in board because of the reduction of peripheral PCIe device, more circuits can be burn-in in the same burn-in high-temperature box, and test cost is saved.

The application provides a tensor data exchange circuit, a data stream processing device and a method. The tensor data exchange circuit is used for a data stream processor and comprises a first non-blocking full permutation component and a second non-blocking full permutation component. The first non-blocking full permutation component and the second non-blocking full permutation component are used for performing data format conversion on a plurality of sub-data blocks split from input data, performing intra-block data exchange and inter-block data exchange, and outputting data meeting target component format requirements. The first non-blocking full permutation component performs intra-block data exchange on the sub-data blocks. The second non-blocking full permutation component performs inter-block data exchange on the plurality of sub-data blocks.

A Provider Edge (PE) router includes a plurality of ports configured to connect to one or more Customer Edge (CE) devices, wherein the plurality of ports are in an Ethernet Virtual Private Network (EVPN) with a second PE router having a second plurality of ports; a static connection configured to connect to the second plurality of ports in the second PE router; and switching circuitry connected to and configured to switch traffic between the plurality of ports, the static connection, and an Internet Protocol (IP) interface connected to an external network, wherein the EVPN is confined to dual homing and protection functionality in the dual homing is performed based on settings in the switching circuitry.

The application relates to a driving circuit of a display panel, the display panel and a display device. The driving circuit comprises a plurality of gate lines and a timing controller. The pixel architecture of the display panel is a double-gate architecture. In the driving circuit, the gate lines correspond to scanning lines one by one. The gate lines are used for providing scanning signals to the scanning lines. An output switching circuit is arranged between a gate line G4n+2 and a gate line G4n+3, n is an integer greater than or equal to 0, the timing controller is connected with the output switching circuit, and the output switching circuit is used for switching the outputs of the gate line G4n+2 and the gate line G4n+3 when receiving a double-line gate function selection signal sent by the timing controller. The application exchanges the outputs of the gate line G4n+2 and the gate line G4n+3, so that the DRD architecture does not misfire when performing double-line gate output, perfectly adapts to the double-line gate function, and solves the technical problem that the double-gate architecture misfires when the double-line gate function is started.

Provided are a display device and a networking method thereof. The display device includes a hub, a universal serial bus (USB) port, a switching circuit, a network interface controller (NIC), and a display control device. The switching circuit is controlled by a control signal. In response to the control signal being in a first state, the USB port is connected to a network through the hub, the switching circuit, and the NIC. In response to the control signal being in a second state, the display control device is connected to the network through the switching circuit and the NIC.

A semiconductor circuit includes a first pad, a second pad, swapping circuit, and an internal circuit. The internal circuit receives a first external signal and a second external signal, and generates a first internal signal and a second internal signal. Based on master information and swapping information, the swapping circuit couples the internal circuit to one of first and second pads to provide a path through which the first internal signal is output and a path through which the first external signal is received, and couples the internal circuit to the other of the first and second pads to provide a path through which the second internal signal is output and a path through which the second external signal is received.

The present invention discloses a method for controlling a pass-through mode of a PCIe switching circuit, and belongs to the field of integrated circuit design. The present invention sets an input-end switching control register and an output-end switching control register for each port inside the PCIe switching circuit, and controls the switching modes of the input port and the output port in sections, so that the user can perform differentiated switching control on the transaction packets entering or outputting from different ports of the PCIe switching circuit, thereby improving the flexibility of the application of the PCIe switching circuit and thus improving the overall switching performance of the system. The present invention enables the switching transactions entering from the same input port to adopt different switching modes for different output ports by setting the output-end switching control registers of different output ports differently; in addition, the switching transactions inputted from different ports and outputted from the same port can adopt different switching modes by setting the input-end switching control registers of different input ports differently.

An electronic device used in a wireless communication network is wirelessly coupled between an access point device and a station device, and it comprises a receiver circuit, a decryption circuit, an address swap circuit, an encryption circuit, and a transmitter circuit. The receiver circuit receives a wireless packet. The decryption circuit decrypts the received wireless packet to generate a decrypted wireless packet. The address swap circuit changes information of at least one MAC address recorded in a MAC header of the decrypted wireless packet to generate an address-swapped packet so as to disguise itself as the access point device or the station device. The encryption circuit encrypts the address-swapped packet to generate an encrypted packet. The transmitter circuit sends the encrypted packet into the air.

In one aspect, the invention relates to an integrated circuit device. The integrated circuit device includes an active device level and a frontside interconnect structure arranged at a frontside of the active device level and a backside interconnect structure arranged at a backside of the active device level. The integrated circuit device includes a plurality of circuit blocks and a data communication circuit configured to transmit data between the plurality of circuit blocks. The data communication circuit includes a plurality of switch circuits. Each circuit block is connected to the data communication circuit through the switch circuits. The data communication circuit further includes a plurality of data communication channels interconnecting the plurality of switch circuits and including a plurality of backside interconnects arranged in one or more interconnect layers of the backside interconnect structure.