31 results about "Interchange circuit" patented technology

A networking device and networking method for use in industrial automation applications. The networking device includes redundant circuitry that can allow the networking device to continue normal operation in the event of a failure that occurs with hardware of the networking device. The networking device includes both primary and secondary network switch circuits, and associated components. The networking device can be an advanced physical layer (APL) switch that interfaces with APL field devices.

A repeater device as switch node in a wireless communication system, includes a donor antenna that obtains a first beam of RF signals from an upstream neighboring node. The repeater device further includes a switch circuit that detects a label in a preamble of each data frame of a plurality of data frames carried by first beam of RF signals independent of decoding other header information and user data in each data frame and determines routing decisions for the plurality of data frames based on the detected label in each data frame. The plurality of data frames is then switched, via a RF switching fabric, based on the detected label in each data frame such that each data frame is routed to a corresponding service phased antenna array of the plurality of service phased antenna arrays for communication via a plurality of service phased antennas.

A first layer one link aggregation master comprises a first port coupled to receive customer traffic; a first channel; a second channel; an aggregation engine coupled to the first and second channels; a first switch circuit coupled to the first port and to the first channel, and configured to communicate the customer traffic from the first port over the first channel to the aggregation engine, the aggregation engine including a splitter circuit configured to use layer one information to segment at least a portion of the customer traffic into a first virtual container and a second virtual container, the aggregation engine further including an encapsulation circuit configured to encapsulate the second virtual container using Ethernet standards for transport over the second channel; a radio access card configured to generate an air frame based on the first virtual container for wireless transmission over a first wireless link of a link aggregation group to the receiver; and a second switch circuit coupled to the second channel, and configured to communicate the Ethernet-encapsulated second virtual container over an Ethernet cable to a slave for wireless transmission over a second wireless link of the link aggregation group to the receiver.

A semiconductor die defect detection device including a current mirror providing a first current on its first output and a second current on its second output, the first and second currents being identical, a swap circuit having a first terminal connected to the first output of the current mirror, a second terminal connected to the second output of the current mirror, a third terminal and a fourth terminal. The device also includes a die ring circuitry disposed at edges of the semiconductor die including a first plurality of segments disposed on a first leg of the die ring circuitry, and a second plurality of segments disposed on a second leg of the die ring circuitry. The device further includes a voltage comparator including a positive input terminal, a negative input terminal and an output terminal, and an adjustable resistor.

A repeater device as switch node in a wireless communication system, includes a donor antenna that obtains a first beam of RF signals from an upstream neighboring node. The repeater device further includes a switch circuit that detects a label in a preamble of each data frame of a plurality of data frames carried by first beam of RF signals independent of decoding header information and user data in each data frame. The plurality of data frames is then switched, via an RF switching fabric, based on the detected label in each data frame such that each data frame is routed to a corresponding service phased antenna array of the plurality of service phased antenna arrays for communication via a plurality of service phased antennas. The switch circuit further generates control signals corresponding to the switched plurality of data frames and transmit the control signals to the RF switching fabric.

A system includes a system-on-chip containing a variety of agents configured to generate data transactions, a communication network configured to transfer transactions between two or more of the agents, a variety of network switches, and a bandwidth control circuit. The network switching circuits can be coupled to the agents and to the network. One of the network switches can be configured to estimate the bandwidth requirements for transactions to be sent through the network switch in an upcoming window.The bandwidth control circuit can be configured to limit network power consumption by determining a bandwidth budget using a network power budget for the upcoming time window and by generating a global bandwidth forecast using estimated bandwidth requirements received from the network switches. The bandwidth control circuit can also be configured to allocate the bandwidth budget among the network switches using the global bandwidth forecast.

The invention provides a tensor data exchange circuit and a data stream processing device and method.The tensor data exchange circuit is used for a data stream processor and comprises a first non-blocking full-arrangement assembly and a second non-blocking full-arrangement assembly; performing data format conversion of in-block data exchange and inter-block data exchange on a plurality of sub-data blocks split by input data through the first non-blocking full-arrangement component and the second non-blocking full-arrangement component so as to output data meeting the format requirement of a target component; wherein the first non-blocking full-arrangement component is used for carrying out in-block data exchange on the sub-data blocks; and the second non-blocking full-arrangement component performs inter-block data exchange on the plurality of sub-data blocks.

The utility model discloses a radio station voice switching system, comprising at least one short-wave radio station which receives and sends far-end voice data through an HF wireless channel; the at least one ultra-short wave radio station is used for receiving and sending far-end voice data through a VHF (very high frequency) or UHF (ultra high frequency) wireless channel; the network voice switching device comprises a network switching board, a switching board and a power supply module, the switching board is connected with the network switching board through a connector, the network switching board comprises an MCU core module, a serial port circuit and a switching circuit, and the network switching board is used for processing and forwarding voice data. The short-wave radio station and the ultra-short-wave radio station are both in communication connection with the network voice switching device. The radio station voice switching system provided by the utility model can realize automatic switching and control of voice services between a short-wave radio station and an ultra-short-wave radio station, and improves communication efficiency and flexibility.

An apparatus and method for reducing the memory bandwidth of executing machine learning models. A computing system includes two or more processing nodes, each including at least one or more processors and a corresponding local memory. Switch circuitry communicates with at least the local memories and a system memory of the computing system. The switch includes multiple direct memory access (DMA) interfaces. Each of one or more processing nodes stores multiple embedding rows of embedding tables. A processor of the processing node identifies two or more embedding rows as source operands of a reduction operation. The switch executes memory access requests to retrieve data of the two or more embedding rows from the corresponding local memory, and generates a result by performing the reduction operation. The switch sends the result to the local memory.

An apparatus includes a system on chip including a plurality of agents configured to generate data transactions, a communication network configured to pass transactions between two or more of the agents, a plurality of network switches, and a bandwidth adjustment circuit. The network switching circuitry may be coupled to a proxy and to a network. One of the network switches may be configured to estimate bandwidth requirements for transactions to be communicated via the network switch in an upcoming window. The bandwidth adjustment circuitry may be configured to regulate power consumption of the network by determining a bandwidth budget using a network power budget for an upcoming time window and determining a global bandwidth prediction using an estimated bandwidth demand received from the network switch. The bandwidth adjustment circuitry may also be configured to allocate a bandwidth budget among the network switches using the global bandwidth prediction.

The application discloses a kind of non-transparent bridge PCIe exchange circuit dynamic burn-in device and method, adopt root complex CPU, endpoint device, port mode configuration line, port interconnection bus and device state indication line, cover the physical layer of circuit, data link layer and transaction layer and non-transparent bridge address conversion and exchange function, so that circuit is carried out dynamic burn-in according to normal working frequency and bus interface rate during burn-in;The application does not need to be externally connected root complex CPU and numerous PCIe endpoint devices for each non-transparent bridge PCIe exchange circuit, and only one root complex CPU is needed on the whole burn-in board, the connection mode of root complex CPU greatly saves the cost of components on burn-in board;The application improves the density of burn-in device on the same area burn-in board because of the reduction of peripheral PCIe device, more circuits can be burn-in in the same burn-in high-temperature box, and test cost is saved.

The application provides a tensor data exchange circuit, a data stream processing device and a method. The tensor data exchange circuit is used for a data stream processor and comprises a first non-blocking full permutation component and a second non-blocking full permutation component. The first non-blocking full permutation component and the second non-blocking full permutation component are used for performing data format conversion on a plurality of sub-data blocks split from input data, performing intra-block data exchange and inter-block data exchange, and outputting data meeting target component format requirements. The first non-blocking full permutation component performs intra-block data exchange on the sub-data blocks. The second non-blocking full permutation component performs inter-block data exchange on the plurality of sub-data blocks.

A Provider Edge (PE) router includes a plurality of ports configured to connect to one or more Customer Edge (CE) devices, wherein the plurality of ports are in an Ethernet Virtual Private Network (EVPN) with a second PE router having a second plurality of ports; a static connection configured to connect to the second plurality of ports in the second PE router; and switching circuitry connected to and configured to switch traffic between the plurality of ports, the static connection, and an Internet Protocol (IP) interface connected to an external network, wherein the EVPN is confined to dual homing and protection functionality in the dual homing is performed based on settings in the switching circuitry.

The application relates to a driving circuit of a display panel, the display panel and a display device. The driving circuit comprises a plurality of gate lines and a timing controller. The pixel architecture of the display panel is a double-gate architecture. In the driving circuit, the gate lines correspond to scanning lines one by one. The gate lines are used for providing scanning signals to the scanning lines. An output switching circuit is arranged between a gate line G4n+2 and a gate line G4n+3, n is an integer greater than or equal to 0, the timing controller is connected with the output switching circuit, and the output switching circuit is used for switching the outputs of the gate line G4n+2 and the gate line G4n+3 when receiving a double-line gate function selection signal sent by the timing controller. The application exchanges the outputs of the gate line G4n+2 and the gate line G4n+3, so that the DRD architecture does not misfire when performing double-line gate output, perfectly adapts to the double-line gate function, and solves the technical problem that the double-gate architecture misfires when the double-line gate function is started.

Provided are a display device and a networking method thereof. The display device includes a hub, a universal serial bus (USB) port, a switching circuit, a network interface controller (NIC), and a display control device. The switching circuit is controlled by a control signal. In response to the control signal being in a first state, the USB port is connected to a network through the hub, the switching circuit, and the NIC. In response to the control signal being in a second state, the display control device is connected to the network through the switching circuit and the NIC.

An electronic device used in a wireless communication network is wirelessly coupled between an access point device and a station device, and it comprises a receiver circuit, a decryption circuit, an address swap circuit, an encryption circuit, and a transmitter circuit. The receiver circuit receives a wireless packet. The decryption circuit decrypts the received wireless packet to generate a decrypted wireless packet. The address swap circuit changes information of at least one MAC address recorded in a MAC header of the decrypted wireless packet to generate an address-swapped packet so as to disguise itself as the access point device or the station device. The encryption circuit encrypts the address-swapped packet to generate an encrypted packet. The transmitter circuit sends the encrypted packet into the air.

In one aspect, the invention relates to an integrated circuit device. The integrated circuit device includes an active device level and a frontside interconnect structure arranged at a frontside of the active device level and a backside interconnect structure arranged at a backside of the active device level. The integrated circuit device includes a plurality of circuit blocks and a data communication circuit configured to transmit data between the plurality of circuit blocks. The data communication circuit includes a plurality of switch circuits. Each circuit block is connected to the data communication circuit through the switch circuits. The data communication circuit further includes a plurality of data communication channels interconnecting the plurality of switch circuits and including a plurality of backside interconnects arranged in one or more interconnect layers of the backside interconnect structure.

Examples described herein relate to a switch circuitry that includes circuitry to determine if a received packet comprises a control packet; circuitry to determine congestion metrics based on receipt of at least one control packet, wherein the at least one control packet comprises a Request To Send (RTS) or Clear To Send (CTS); and circuitry to transmit at least one of the congestion metrics in at least one packet to a sender and / or receiver network interface device.

In an example implementation, a network device includes first switch circuitry associated with a first set of physical ports and second switch circuitry associated with a second set of physical ports. The first and second sets of physical ports may collectively form a combined set of physical ports. A communication link may couple the first switch circuitry and the second switch circuitry. A mapping of the first set of physical ports and the second set of physical ports to single set of virtual ports may be stored. One or more processors are configured to receive a transmission on a first physical port of the combined set of physical ports, access the mapping to determine a first virtual port of the single set of virtual ports that corresponds to the first physical port, and generate an indication of the first virtual port as a communication port for the transmission.

An adapter receivable by a network device connector may include a corresponding mating connector and switching circuitry. Different lanes of the mating connector, and consequently different lanes of the network device connector, may be accessible via the switching circuitry at corresponding test connectors. The lanes for access may be selectable using input devices of the adapter. Configured in this manner, external equipment such as test equipment may selectively access the lanes of the network device connector through the adapter.

We provide a reversing device and a plating production line. [Solution] The inversion device is used in a plating production line, which includes two horizontal plating devices. The inversion device is installed between the two horizontal plating devices and includes a machine frame, a feeding mechanism and an inversion mechanism installed on the machine frame. The feeding mechanism has a horizontal transport surface for horizontally placing circuit boards. Circuit boards plated by one horizontal plating device enter the horizontal transport surface and are transported horizontally through the feeding mechanism to the other horizontal plating device. During transport, the inversion mechanism flips the circuit board on the horizontal transport surface so that the plating transport mechanisms of the two horizontal plating devices each sandwich the circuit board on its opposing sides, and also swaps the positions of the two opposing sides of the circuit board. This makes the plating layer of the circuit board, which has been plated twice by the two horizontal plating devices, more uniform and effectively improves the production quality of the circuit boards.

A system includes a first printed circuit board, a temperature sensor, a switching circuit, and a controller. The temperature sensor is configured to measure the temperature of at least one area of ​​the first printed circuit board. The switching circuit is disposed on the first printed circuit board. The controller is configured to trigger the switching circuit to shut off power to the first printed circuit board based at least in part on a temperature detected by the temperature sensor above a temperature threshold. Since known power protection methods rely on interrupting power when maximum power is sensed, these methods may have blind spots for certain areas of the first printed circuit board. The system provided herein can interrupt power faster than known power protection methods.

A phase error compensation circuit and a method for compensating a phase error between a reference clock and a feedback clock are provided. The phase error compensation circuit includes a first programmable delay circuit, a second programmable delay circuit and at least one swapping circuit. The first programmable delay circuit provides a first delay. The second programmable delay circuit provides a second delay. At a present cycle, the first delay is unchanged, wherein the swapping circuit applies the first delay to the feedback clock for generating a compensated feedback clock and applies the second delay to the reference clock for generating a compensated reference clock. At a next cycle, the second delay is unchanged, where the swapping circuit applies the second delay to the feedback clock for generating the compensated feedback clock and applies the first delay to the reference clock for generating the compensated reference clock.

Exemplary embodiments include RF integrated circuit (RFIC) chips including programmable on-chip element swapping circuitry, channel swapping circuitry, and / or phase rotation circuitry to allow a common software implementation or parameter computation to be used across multiple products having different arrangements and orientations of RFICs and elements.

This invention discloses a paper-based cellular carrier-based intelligent reconfigurable metasurface structure communication module, a multi-user high-efficiency collaborative communication system, and its communication method, belonging to the field of electronic communication antenna design. It includes a reconfigurable metasurface structure, a switching circuit, and a control unit. The reconfigurable metasurface structure comprises a metasurface radiating array and a planar lens. Multiple radiating elements of the metasurface radiating array radiate electromagnetic waves in different spatial directions. The planar lens, positioned along the electromagnetic wave radiation path of the metasurface radiating array, has a gradually changing refractive index distribution structure, enabling it to refract and focus electromagnetic waves from different spatial directions onto radiating elements at different locations. Multiple switching switches in the switching circuit control the selection and deactivation of different radiating elements. The control unit is communicatively connected to the switching circuit to control the corresponding switching switches. While maintaining high aperture efficiency and broadband characteristics, it achieves low-overhead concurrent beamforming in multiple directions and at multiple nodes.

An apparatus includes a system-on-chip that includes a plurality of agents configured to generate data transactions, a communication network configured to transfer transactions between two or more of the agents, a plurality of network switches, and a bandwidth regulation circuit. The network switching circuits may be coupled to the agents and to the network. One of the network switches may be configured to estimate a bandwidth need for transactions to be sent via the network switch in an upcoming window. The bandwidth regulation circuit may be configured to moderate power consumption of the network by determining a bandwidth budget using a network power budget for the upcoming time window, and determining a global bandwidth forecast using estimated bandwidth needs received from the network switches. The bandwidth regulation circuit may also be configured to allocate, using the global bandwidth forecast, the bandwidth budget among the network switches.

An apparatus includes a system-on-chip that includes a plurality of agents configured to generate data transactions, a communication network configured to transfer transactions between two or more of the agents, a plurality of network switches, and a bandwidth regulation circuit. The network switching circuits may be coupled to the agents and to the network. One of the network switches may be configured to estimate a bandwidth need for transactions to be sent via the network switch in an upcoming window. The bandwidth regulation circuit may be configured to moderate power consumption of the network by determining a bandwidth budget using a network power budget for the upcoming time window, and determining a global bandwidth forecast using estimated bandwidth needs received from the network switches. The bandwidth regulation circuit may also be configured to allocate, using the global bandwidth forecast, the bandwidth budget among the network switches.

This invention belongs to the field of FFT computation acceleration technology, specifically relating to an adaptive FFT operation processor module for handling large amounts of data, including an address generation module, a data rearrangement unit, a twiddle factor storage module, an FFT computation module, and a control module; the FFT computation module includes m-row radix-2 arrays arranged side-by-side. k The MDC module includes a data rearrangement unit comprising a read / write data storage module and a data preprocessing module. The read / write data storage module consists of multiple memories. The data preprocessing module consists of multiple parallel branch switching circuits and multiple shuffling units of varying depths. The twiddle factor storage module stores fixed constant twiddle factors and reuses them based on the number of calculation points. The address generation module uses a program counter to generate address sequences for data read / write. The control module controls the execution of FFT calculations and can adapt to different FFT calculation requirements. This improves the utilization rate of the butterfly operation unit and the overall computational throughput of the architecture.

The application designs a laser wireless energy transmission photovoltaic receiving and generating system which can be assembled, comprising a laser emitting system and a laser receiving system; the application uses a double positioning system, and the precision is higher than that of a single positioning system; the laser detector can screen and identify the light intensity of the laser to protect the internal circuit; the laser collector improves the energy utilization rate to improve the system conversion efficiency; under the tracking of the MPPT maximum power tracking circuit, the system efficiency is maximized; under the DC-DC exchange circuit, voltage stabilization and rectification are realized; under the feedback of the detection and protection output current and voltage system, the charging time is shortened, and the function of adjusting the working distance and the output power in real time according to the needs is completed; with the help of the feedback signal of the detection and protection output current and voltage system, the charging process is more accurate, efficient and intelligent; the application can be applied to unmanned aerial vehicles and various spacecrafts, and effectively solves the problems of short endurance and the need to return to the base for energy supply.