11 results about "Interchange circuit" patented technology

A networking device and networking method for use in industrial automation applications. The networking device includes redundant circuitry that can allow the networking device to continue normal operation in the event of a failure that occurs with hardware of the networking device. The networking device includes both primary and secondary network switch circuits, and associated components. The networking device can be an advanced physical layer (APL) switch that interfaces with APL field devices.

A repeater device as switch node in a wireless communication system, includes a donor antenna that obtains a first beam of RF signals from an upstream neighboring node. The repeater device further includes a switch circuit that detects a label in a preamble of each data frame of a plurality of data frames carried by first beam of RF signals independent of decoding header information and user data in each data frame. The plurality of data frames is then switched, via an RF switching fabric, based on the detected label in each data frame such that each data frame is routed to a corresponding service phased antenna array of the plurality of service phased antenna arrays for communication via a plurality of service phased antennas. The switch circuit further generates control signals corresponding to the switched plurality of data frames and transmit the control signals to the RF switching fabric.

A system includes a system-on-chip containing a variety of agents configured to generate data transactions, a communication network configured to transfer transactions between two or more of the agents, a variety of network switches, and a bandwidth control circuit. The network switching circuits can be coupled to the agents and to the network. One of the network switches can be configured to estimate the bandwidth requirements for transactions to be sent through the network switch in an upcoming window.The bandwidth control circuit can be configured to limit network power consumption by determining a bandwidth budget using a network power budget for the upcoming time window and by generating a global bandwidth forecast using estimated bandwidth requirements received from the network switches. The bandwidth control circuit can also be configured to allocate the bandwidth budget among the network switches using the global bandwidth forecast.

An apparatus and method for reducing the memory bandwidth of executing machine learning models. A computing system includes two or more processing nodes, each including at least one or more processors and a corresponding local memory. Switch circuitry communicates with at least the local memories and a system memory of the computing system. The switch includes multiple direct memory access (DMA) interfaces. Each of one or more processing nodes stores multiple embedding rows of embedding tables. A processor of the processing node identifies two or more embedding rows as source operands of a reduction operation. The switch executes memory access requests to retrieve data of the two or more embedding rows from the corresponding local memory, and generates a result by performing the reduction operation. The switch sends the result to the local memory.

An electronic device used in a wireless communication network is wirelessly coupled between an access point device and a station device, and it comprises a receiver circuit, a decryption circuit, an address swap circuit, an encryption circuit, and a transmitter circuit. The receiver circuit receives a wireless packet. The decryption circuit decrypts the received wireless packet to generate a decrypted wireless packet. The address swap circuit changes information of at least one MAC address recorded in a MAC header of the decrypted wireless packet to generate an address-swapped packet so as to disguise itself as the access point device or the station device. The encryption circuit encrypts the address-swapped packet to generate an encrypted packet. The transmitter circuit sends the encrypted packet into the air.

In one aspect, the invention relates to an integrated circuit device. The integrated circuit device includes an active device level and a frontside interconnect structure arranged at a frontside of the active device level and a backside interconnect structure arranged at a backside of the active device level. The integrated circuit device includes a plurality of circuit blocks and a data communication circuit configured to transmit data between the plurality of circuit blocks. The data communication circuit includes a plurality of switch circuits. Each circuit block is connected to the data communication circuit through the switch circuits. The data communication circuit further includes a plurality of data communication channels interconnecting the plurality of switch circuits and including a plurality of backside interconnects arranged in one or more interconnect layers of the backside interconnect structure.

A counting circuit and operating system provide an output count value. A switching circuit provides one of first and second input signals as a first output signal and the other of the first and second input signals as a second output signal in response to a first select signal. A mode select circuit provides the first and second output signals as first and second channel signals or the first and second output signals as third and fourth channel signals in response to a second select signal. A first processing circuit adjusts a first count value when the first channel signal or the second channel signal changes from a first level to a second level. A second processing circuit adjusts a second count value when the third channel signal changes from the first level to the second level. An output circuit provides the first or second count value as the output count value.

Examples described herein relate to a switch circuitry that includes circuitry to determine if a received packet comprises a control packet; circuitry to determine congestion metrics based on receipt of at least one control packet, wherein the at least one control packet comprises a Request To Send (RTS) or Clear To Send (CTS); and circuitry to transmit at least one of the congestion metrics in at least one packet to a sender and / or receiver network interface device.

An adapter receivable by a network device connector may include a corresponding mating connector and switching circuitry. Different lanes of the mating connector, and consequently different lanes of the network device connector, may be accessible via the switching circuitry at corresponding test connectors. The lanes for access may be selectable using input devices of the adapter. Configured in this manner, external equipment such as test equipment may selectively access the lanes of the network device connector through the adapter.

This invention discloses a paper-based cellular carrier-based intelligent reconfigurable metasurface structure communication module, a multi-user high-efficiency collaborative communication system, and its communication method, belonging to the field of electronic communication antenna design. It includes a reconfigurable metasurface structure, a switching circuit, and a control unit. The reconfigurable metasurface structure comprises a metasurface radiating array and a planar lens. Multiple radiating elements of the metasurface radiating array radiate electromagnetic waves in different spatial directions. The planar lens, positioned along the electromagnetic wave radiation path of the metasurface radiating array, has a gradually changing refractive index distribution structure, enabling it to refract and focus electromagnetic waves from different spatial directions onto radiating elements at different locations. Multiple switching switches in the switching circuit control the selection and deactivation of different radiating elements. The control unit is communicatively connected to the switching circuit to control the corresponding switching switches. While maintaining high aperture efficiency and broadband characteristics, it achieves low-overhead concurrent beamforming in multiple directions and at multiple nodes.

This invention belongs to the field of FFT computation acceleration technology, specifically relating to an adaptive FFT operation processor module for handling large amounts of data, including an address generation module, a data rearrangement unit, a twiddle factor storage module, an FFT computation module, and a control module; the FFT computation module includes m-row radix-2 arrays arranged side-by-side. k The MDC module includes a data rearrangement unit comprising a read / write data storage module and a data preprocessing module. The read / write data storage module consists of multiple memories. The data preprocessing module consists of multiple parallel branch switching circuits and multiple shuffling units of varying depths. The twiddle factor storage module stores fixed constant twiddle factors and reuses them based on the number of calculation points. The address generation module uses a program counter to generate address sequences for data read / write. The control module controls the execution of FFT calculations and can adapt to different FFT calculation requirements. This improves the utilization rate of the butterfly operation unit and the overall computational throughput of the architecture.