Image processing method and image processing device

Abstract

The invention provides an image processing method and an image processing device, which are realized by using a field programmable gate array (FPGA), of a neural network algorithm for image processing. The image processing method comprises the steps that a first convolution calculation unit performs a first layer of convolution calculation on input image data so as to generate a first layer of feature data; the first layer of feature data is stored into a storage unit; and a second convolution calculation unit reads the first layer of feature data from the storage unit, and executes a preset number of layers of convolution calculation and generates a convolution calculation result for the input image data, wherein the corresponding calculation result is stored into the storage unit at the end of each layer of convolution calculation, and the first convolution calculation unit and the second convolution calculation unit are configured by the field programmable gate array.

Description

technical field [0001] The present disclosure relates to the field of image processing, and more particularly, the present disclosure relates to an image processing method and an image processing device for implementing a neural network algorithm for image processing by using a Field Programmable Gate Array (FPGA). Background technique [0002] Object detection is a basic research topic in the field of computer image processing, and it has broad application prospects in many aspects such as face recognition, security monitoring and dynamic tracking. Target detection refers to the detection and recognition of a specific target (such as a human face) in any frame or continuous frame images, and returns the position and size information of the target, such as outputting a bounding box surrounding the target. Neural networks are a tool for large-scale, multi-parameter optimization. Relying on a large amount of training data, the neural network can learn hidden features that are...

AI Technical Summary

Problems solved by technology

At present, there are two main disadvantages in the scheme of implementing the CNN algorithm by using a field programmable gate array: the first is that a large number of digital signal processor (DSP) resources are used for parallel computing, because the number of DSPs inside the field programmable gate array is extremely limited ( Generally hundreds), so the lack of DSP resources limits the amount of parallel computing per unit cycle; the second is that most of them are written in high-level synthesis tools such as C language, and then optimized with low-level hardware language, and use 8-bit specific point Or floating-point numbers represent parameters, and finally realize the general CNN algorithm

Although this architectural approach can reconstruct the CNN network, it wastes field programmable gate array resources and cannot fully utilize the computing power of field programmable gate arrays.

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