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Caching method and device for microcontroller

A high-speed cache and micro-controller technology, applied in the direction of instruments, memory systems, electrical digital data processing, etc., can solve the problems of low hit rate of instruction data and inflexible usability of high-speed cache

Inactive Publication Date: 2017-04-05
SHENZHEN BOJUXING IND DEV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In view of this, the embodiments of the present invention provide a method and device for a microcontroller cache, aiming to solve the problem that the cache in the prior art does not have flexible usability, causing the microcontroller to read instruction data from the cache and hit low rate problem

Method used

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  • Caching method and device for microcontroller
  • Caching method and device for microcontroller
  • Caching method and device for microcontroller

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Embodiment 1

[0021] figure 1 The implementation flow of the microcontroller cache method provided by Embodiment 1 of the present invention is shown, and the implementation flow is described in detail as follows:

[0022] In step S101, the address information of the instruction data is acquired;

[0023] In the embodiment of the present invention, when the microcontroller reads the instruction data, it sends the address information of the instruction data to the cache to determine whether the instruction data has been cached in the cache.

[0024] In step S102, it is detected whether the address information of the instruction data exists in the static random access memory SRAM;

[0025] In the embodiment of the present invention, the SRAM is used to store the address information of the instruction data cached in the cache.

[0026] Exemplarily, a 4K-byte cache is used, 4K bytes are 1K words, if the cache caches 4 words at a time, it needs to store 256 address information, and one address ...

Embodiment 2

[0039] figure 2 The implementation flow of the microcontroller cache method provided by Embodiment 2 of the present invention is shown, and the implementation flow is described in detail as follows

[0040] In step S201, a plurality of address control registers for configuring the address space of the cache memory are set;

[0041] In the embodiment of the present invention, a plurality of address control registers are used to configure the address space of the cache memory, and the address information of the instruction data in the flash memory is allocated to the address space of the cache memory to determine whether the instruction data Caching is required. For example, if one of the address control registers configures the address space of the cache as 100-4ff, then any instruction data belonging to the address information in this address range can be cached.

[0042] In step S202, the control enable register configures the enable bit of the cache as 1 to enable the cach...

Embodiment 3

[0063] image 3 A schematic diagram of the composition of the microcontroller cache device provided by the third embodiment of the present invention is shown. For the convenience of description, only the parts related to the embodiment of the present invention are shown, and the details are as follows:

[0064] An acquisition module 301, configured to acquire address information of instruction data;

[0065] A detection module 302, configured to detect whether address information of the instruction data exists in the static random access memory SRAM;

[0066] The processing module 303 is used to read the data of N words from the flash memory when the address information of the instruction data does not exist in the SRAM, and store the data of the N words read into the cache memory wherein, the address information of the N words of data is stored in the SRAM, and one word of the instruction data is returned to the microcontroller, wherein, N is an integer greater than zero.

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Abstract

The invention belongs to the field of microcontroller technology and provides a caching method and device for a microcontroller. The method comprises the steps that address information of command data is acquired; whether the address information of the command data exists in a static random access memory (SRAM) or not is detected; when the address information of the command data does not exist in the SRAM, N-character data is read from a flash memory, the read N-character data is stored into a cache, address information of the N-character data is stored into the SRAM, and one-character command data is returned to the microcontroller, wherein N is an integer greater than zero. Through the caching method and device, the problem that in the prior art, the cache does not have flexible usability, and consequently the hit rate is low when the microcontroller reads the command data from the cache is effectively solved.

Description

technical field [0001] The invention belongs to the technical field of microcontrollers, and in particular relates to a method and device for cache memory of microcontrollers. Background technique [0002] With the continuous improvement of the technology level, the integration of the chip is getting higher and higher, and the processing speed of the microcontroller is getting faster and faster. When designing a microcontroller based on flash memory, because the operating frequency of the flash memory can only reach 20-30MHZ, its operating speed limits the speed at which the microcontroller can read instruction data. In the prior art, the speed at which the microcontroller reads instruction data can be increased by adding a cache between the microcontroller and the flash memory. However, the cache in the prior art does not have flexible usability, and the microcontroller reads instruction data from the cache with a low hit rate. [0003] Therefore, it is necessary to propo...

Claims

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Application Information

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IPC IPC(8): G06F12/0875G06F12/0877G06F12/0893
Inventor 许建昆叶媲舟黎冰涂柏生
Owner SHENZHEN BOJUXING IND DEV
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