A clock voltage doubler circuit and charge pump

Abstract

The application discloses a clock voltage doubling circuit and a charge pump. The clock voltage doubling circuit includes: an input unit, a first buffer unit and a second buffer unit. The clock voltage doubling circuit connects the first transistor and the fourth transistor of the logic device with a lower threshold voltage in series for the second transistor and the third transistor of the input and output device respectively, and connects the sixth transistor and the seventh transistor of the input and output device in series with a lower threshold voltage. The fifth transistor and the eighth transistor of the small logic device, so that when the input operating voltage swing is small, so that when the first voltage and the second voltage output by the input unit are small, the logic device with a small threshold voltage can be turned on normally, In this way, the normal opening of the input and output devices is ensured, and the clock voltage doubler circuit can work normally. At the same time, it is ensured that the voltage difference between any two poles of the logic device transistor does not exceed the working voltage during the working process, and the protection of the logic device transistor is realized. The normal operation of the clock voltage doubler circuit is ensured.

Description

technical field [0001] The present application relates to the technical field of clock voltage doubling circuit design, and more specifically, to a clock voltage doubling circuit and a charge pump. Background technique [0002] Charge pumps are widely used in high-voltage devices, and their basic design concept is to couple charge from the charge pump clock to each charge pump node. Higher coupling voltages will result in higher output voltages with fewer charge pump stages. The clock signal is mainly provided for the charge pump through a clock voltage doubler circuit. figure 1 It is a schematic circuit structure diagram of a clock voltage doubling circuit in the prior art. The clock voltage doubling circuit mainly includes an input stage 10, a first buffer stage 20 and a second buffer stage 30, wherein the input stage 10 is composed of a first A capacitor C1, a second capacitor C2, a first transistor T1, and a second transistor T2 are formed. The first buffer stage 20 is...

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Problems solved by technology

[0006] In order to solve the above technical problems, the present invention provides a clock voltage doubler circuit and a charge pump to solve the problem that the clock voltage doubler circuit functions when the process angle and working conditions of the transistor are relatively harsh and the input operating voltage swing is small. abnormal problem

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