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System and method for adjusting duty cycle in clock signals

A clock signal, duty cycle technology, applied in the field of duty cycle systems, can solve problems such as reduction

Inactive Publication Date: 2017-05-10
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This reduces the level of unwanted sub-harmonics in the multiplied frequency output from the frequency multiplier circuit

Method used

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  • System and method for adjusting duty cycle in clock signals
  • System and method for adjusting duty cycle in clock signals

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Embodiment Construction

[0011] Now, the present disclosure will be described more fully hereinafter with reference to the accompanying drawings that illustrate embodiments of the disclosure. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the devices and methods to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals denote the same elements throughout.

[0012] It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another eleme...

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Abstract

Provided are a system and method for adjusting duty cycle in clock signals. A device and method are disclosed. The device and method allow the clock signal of a wireless communication device to produce an oscillation with a 50% duty cycle. The device and method allows quick convergence to a 50% duty cycle after power up and also provides stability of the duty cycle across variations in ambient temperature and power supply fluctuations. The device includes, but is not limited to a buffer, a first inverter electrically coupled to the buffer, a second inverter electrically coupled to the first inverter, and a differential integrator, wherein a first output of the first inverter is electrically coupled to a first input of the differential integrator, wherein a second output of the second inverter is electrically coupled to a second input of the differential integrator, and wherein a third output of the differential integrator is electrically connected to the buffer.

Description

[0001] This application claims priority to U.S. Provisional Patent Application No. 62 / 250,274 and U.S. Provisional Patent Application No. 62 / 251,842, filed with the U.S. Patent and Trademark Office on November 3, 2015, and No. 6, 2015, respectively, each The contents of the US Provisional Patent Application are hereby incorporated by reference. technical field [0002] The present disclosure relates generally to generating clock signals, and more particularly, to a system and method for adjusting a duty cycle in a clock signal. Background technique [0003] Crystal oscillators, such as temperature compensated crystal oscillators (TCXOs), provide reference frequencies to various phase-locked loops (PLLs) within a typical radio frequency integrated circuit, and also provide clocks to various processors. These PLLs are necessary blocks for radios such as Wi-Fi, cellular, Global Navigation Satellite System (GNSS) and Bluetooth. [0004] As communication systems evolve, there is...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K5/156
CPCH03K5/1565H03K3/017H03B5/32H03K3/0315H03K5/00006
Inventor 刘宗耀
Owner SAMSUNG ELECTRONICS CO LTD