Finfet isolation structure and manufacturing method thereof

Abstract

A semiconductor device includes a semiconductor substrate and a semiconductor fin on the semiconductor substrate, wherein the semiconductor fin has a fin isolation structure at a common boundary shared by two cells. The fin isolation structure has a dielectric portion extending from the top of the semiconductor fin to a stop layer on the semiconductor substrate. The dielectric portion divides the semiconductor fin into two parts of the semiconductor fin. Embodiments of the invention also relate to FinFET isolation structures and methods of manufacturing the same.

Description

technical field [0001] Embodiments of the present invention relate to integrated circuit devices, and more particularly, to FinFET isolation structures and fabrication methods thereof. Background technique [0002] As semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), scale down through various technology nodes, device packaging density and device performance are challenged by device layout and isolation. To avoid leakage between adjacent devices (cells), the standard cell layout employs pseudo polysilicon (poly) segments (i.e., OD edge polysilicon on (PODE)). [0003] As the semiconductor IC industry enters nanotechnology process nodes in pursuit of higher device density, higher performance, and lower cost, manufacturing and design challenges have given rise to applications such as Fin Field Effect Transistors (FinFETs). Development of three-dimensional (3D) devices. Advantages of FinFET devices include reduced short channel effe...

AI Technical Summary

Problems solved by technology

However, not all existing FinFET devices and methods of fabricating FinFET devices have been fully satisfactory in employing PODEs that isolate two adjacent devices (cells)

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