A Timing Design Method for Modulation Domain Measurement in Short Time Interval

Abstract

The present invention proposes a short time interval modulation domain measurement sequence design method, including: measurement data output time arrangement unit, each data effective serial parallel structure unit, measurement effective feedback signal generation unit, operation processing unit; the measurement data output time The arrangement unit arranges the data of various parameters in one measurement of each measurement unit in chronological order, and designs each data effective serial-parallel structural unit according to this order; the effective serial-parallel structural unit of each data is the output of each measurement parameter Construct a series-parallel process based on the contextual relationship, select the moment when the last measurement data is output as the end of an effective measurement process; the measurement effective feedback signal generation unit uses the feedback signal to start the measurement unit; the operation processing unit is responsible for the realization of the algorithm The data measured by the two channels of the high and low gates are seamlessly integrated, and the measured data is read through the high-speed interface, and is responsible for the final calculation, processing and display of the data.

Description

technical field [0001] The invention relates to the technical field of testing, in particular to a timing sequence design method for short time interval modulation domain measurement. Background technique [0002] In the field of electronic measurement, with the development and application of pulse modulation, digital modulation, linear modulation, and frequency-agile modulation technologies, higher requirements are placed on modern modulation domain analyzers. In order to meet new requirements, modern modulation domain analysis needs to have measurement requirements such as shorter sampling interval, larger analysis bandwidth, and higher resolution. Modulation domain analysis accurately characterizes the transient characteristics of the signal under test through high-speed continuous measurement without dead zone. The typical measurement sequence diagram is as follows: figure 1 shown. [0003] figure 1 Among them, the synchronous gate Ts is generated after synchronizing ...

AI Technical Summary

Problems solved by technology

However, since the determination of the delay time is still based on the low gate as the time reference, the size of the gate must be greater than ΔT0 to meet the processing of the delay time of ΔT0, that is to say, ΔT0 limits the gate design and cannot be less than ΔT0

Moreover, there is a certain time error in the actual circuit. In the actual test, the value of ΔT0 will fluctuate in a small range according to the time of retriggering. Therefore, the delay time setting should be larger than ΔT0, and the measurement time will be further increased.

[0010] Therefore, according to the method of processing high gate channel data during low gate period and processing low gate channel data during high gate period, the time interval of modern technical solutions for modulation domain analysis is limited to more than 100 ns, or even higher, which also restricts the short time of modulation domain analysis. Interval requirements for frequency-agile and linear-frequency measurements

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