FPGA (Field Programmable Gate Array) circuit and window signal adjustment method

Abstract

The invention provides an FPGA (Field Programmable Gate Array) circuit and a window signal adjustment method. The FPGA circuit comprises a physical layer, a DQS (Data Strobe Signal) GATING circuit, a delay compensation loop, a first circuit and a second circuit, wherein the DQS GATING circuit is connected with the physical layer; the delay compensation loop is connected with the DQS GATING circuit; the first circuit is connected between the physical layer and an external storage; the second circuit is connected between the external storage and the DQS GATING circuit; a window control signal emitted by the physical layer can sequentially pass through the DQS GATING circuit and the delay compensation loop; the DQS GATING circuit is used for adjusting the position of a target window signal relative to a DQS according to the target window signal and the DQS. By adopting the scheme, the window control signal passes through the delay compensation loop, so that the time from emitting a read command by the physical layer to receiving the read command by the external storage and the time from sending the DQS by the external storage to receiving the DQS by the DQS GATING circuit are compensated; through the compensation, when the position of an initial window signal is near the DQS, the window signal can be rapidly adjusted to a reasonable position, and the adjusting efficiency of the window signal is increased.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to an FPGA (Field-Programmable Gate Array, Field Programmable Gate Array) circuit and a window signal adjustment method. Background technique [0002] In DDR (Double Data Rate, double rate synchronous dynamic random access memory) memory, its input and output data are synchronized with the rising and falling edges of the clock, so a bidirectional DQS (Data Strobe) with the same frequency as the clock is required in the read and write operations. Signal, data strobe signal) signal to grab data. This DQS signal is a three-state signal, which is in a high-impedance state when not in use. When the memory receives a read command, the DQS signal will switch to logic low in the previous cycle of data output. When the read command is completed, it will be at the end of the DQS signal. The DQS signal returns to the high-impedance state after half a clock period after a falling edge ...

AI Technical Summary

Problems solved by technology

[0004] The technical problem mainly solved by the present invention is to provide an FPGA circuit and a window signal adjustment method to solve the problems in the prior art that when adjusting the window signal, the adjustment range is relatively large, and the adjustment accuracy and efficiency are relatively low.

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