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Formation method of semiconductor structure

A semiconductor and mask layer technology, applied in the field of formation of semiconductor structures, can solve problems such as the impact of semiconductor structure performance

Active Publication Date: 2019-11-05
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, the existing technology cannot meet this requirement, so that the performance of the formed semiconductor structure is affected

Method used

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  • Formation method of semiconductor structure
  • Formation method of semiconductor structure
  • Formation method of semiconductor structure

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Embodiment Construction

[0029] As mentioned in the background art, in the prior art, when forming the semiconductor structure of the back gate structure and the front gate structure, the gate dielectric layers of the back gate structure and the front gate structure often use the same material and thickness, which affects the performance of the semiconductor structure .

[0030] In an embodiment of the present invention, the gate dielectric layer of the back gate structure and the gate dielectric layer of the front gate structure are respectively formed, so that the back gate structure and the front gate structure in the semiconductor structure have different gate dielectric layers, so as to improve the properties of semiconductor structures.

[0031] In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0032] Please refe...

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Abstract

The invention relates to a formation method of a semiconductor structure. The formation method comprises: a semiconductor substrate including a first semiconductor layer, an insulating layer, a second semiconductor layer are provided; a first mask layer is formed on the surface of the second semiconductor layer; a side wall is formed at the side wall surface of the first mask layer; the second semiconductor layer is etched to form a first groove; a first oxide layer arranged below the sidewall is formed; a first gate material layer filling the first groove and an isolated layer on the surface of the first gate material layer are formed; the first mask layer is etched to form a second mask layer and the second semiconductor layer is etched to form a first initial fin part and a second initial fin part; transverse etching is carried out on the first initial fin part and the second initial fin part; a semiconductor material layer is formed on the side wall surfaces of the first initial fin part and the second initial fin part and a gate dielectric layer is formed on the surface of the semiconductor material layer; a second gate material layer is formed; and graphical processing is carried out on the first gate material layer and the second gate material layer to form a back gate and a front gate. Therefore, the performance of the semiconductor structure can be improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming a semiconductor structure. Background technique [0002] The threshold voltage of a semiconductor device is one of the important parameters of a transistor, and a stable threshold voltage is an important indicator of the good performance of a semiconductor device. At present, one method to adjust the threshold voltage of semiconductor devices is to adjust the doping concentration of the channel region of the transistor, and since the dopant ions in the channel region are usually doped by ion implantation, due to the volatility of the ion implantation process, the channel The dopant ion concentration, depth and other parameters in the channel area will also fluctuate, and the dopant ions are also affected by diffusion, so that the threshold voltage of the transistor cannot be accurately controlled; and as the size of semiconductor devices becomes smalle...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L29/78
CPCH01L29/66795H01L29/785H01L29/7855
Inventor 邓浩
Owner SEMICON MFG INT (SHANGHAI) CORP