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FPGA-based FFT device and method

A butterfly computing and caching technology, applied in the field of digital signals, can solve the problems of multiple FPGA resources and low RAM utilization, and achieve the effects of improving computing speed, improving utilization, and saving resources

Pending Publication Date: 2017-07-21
POTEVIO INFORMATION TECH
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  • Summary
  • Abstract
  • Description
  • Claims
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Problems solved by technology

[0018] The technical problem to be solved by the present invention is: the existing FFT device has low utilization rate of RAM and needs more FPGA resources in the data sequence output

Method used

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  • FPGA-based FFT device and method
  • FPGA-based FFT device and method

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Embodiment Construction

[0059] Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0060] figure 2 A schematic structural diagram of an FPGA-based FFT device according to an embodiment of the present invention is shown.

[0061] Such as figure 2 Shown, the FFT device based on FPGA of the present embodiment comprises:

[0062] Cache module 1, control module 2 and radix-4 butterfly operator 3;

[0063] The control module 2 is connected to the cache module 1 and the radix-4 butterfly operator 3 respectively, and is used to control the input and output of data, and is used to control the data to be cached in the cache module 1 in the form of a ping-pong cache, and is used to control the data to circulate The addressing mode completes the FFT operation in the radix-4 butterfly operator 3;

[0064] Cache module 1 is used to initially input the first 3 / 4 of the data, output the last 3 / 4 of the calculation results, and store the intermed...

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Abstract

The invention relates to an FPGA-based FFT device and method. The device comprises a buffer module, a control module and a radix-4 butterfly operator, wherein the control module is respectively connected to the buffer module and the radix-4 butterfly operator and is used for controlling input and output of data, controlling data to be buffered to the buffer module in a ping-pong buffer manner and controlling the data to complete FFT operation in the radix-4 butterfly operator in a circular addressing manner; the buffer module is used for initially inputting front 3 / 4 of data, outputting back 3 / 4 of operation result and storing an intermediate result; and the radix-4 butterfly operator is used for initially inputting back 1 / 4 of data and outputting front 1 / 4 of operation result. According to the device and the method, the operation speed is improved, and the total depth of an RAM for storing the data is reduced under the condition that the quantity of DSP multiplying units is equal to the quantity of the FFT devices applying radix-4 butterfly operation units.

Description

technical field [0001] The invention relates to the field of digital signals, in particular to an FPGA-based FFT device and method. Background technique [0002] In wireless communication systems, fast Fourier transform (FFT) is often used to transform and analyze the input time-domain signal, and observe the frequency-domain waveform to obtain the frequency-domain characteristics of the signal. OFDM uses inverse discrete Fourier transform and discrete Fourier transform (IDFT / DFT) instead of multi-carrier modulation and demodulation, that is, the IFFT operation is performed on the data to be modulated at the transmitting end to achieve modulation, and the receiving end performs FFT on the received data The operation realizes demodulation, thus greatly reducing the complexity of system realization. [0003] FPGA can well solve the problems of parallelism and speed, and has the characteristics of flexible configuration and easy upgrade. It is a commonly used method to realize...

Claims

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Application Information

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IPC IPC(8): G06F17/14G06F9/355
CPCG06F9/3552G06F17/142
Inventor 王纪宁
Owner POTEVIO INFORMATION TECH
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