Manufacturing method of semiconductor device

Abstract

The invention provides a method for manufacturing a semiconductor device. From the perspective of process integration, the process sequence and flow are optimized. After depositing a buffer layer on the surface of the layer to be polished, at least at the border area between the second area and the first area is formed. Then the layer to be polished in the first zone is thinned, and the layer to be polished in the junction area is completely reserved due to the barrier of the buffer layer. After chemical mechanical polishing, the first zone and the The surface height of the layer to be polished in the second zone is consistent, avoiding the formation of a step difference in the junction area between the first zone and the second zone, thereby improving the uniformity of the layer to be polished in the first zone and the second zone after chemical mechanical polishing, and improving device yield.

Description

technical field [0001] The invention relates to the technical field of integrated circuit manufacturing, in particular to a method for manufacturing a semiconductor device. Background technique [0002] With the rapid development of Ultra Large Scale Integration (ULSI), the manufacturing process of integrated circuits has become more and more complex and refined, and the requirements for electrical stability of semiconductor devices formed on semiconductor substrates are also getting higher and higher. . However, in the manufacturing process of semiconductor devices, the undulations on the surface of the film layer have a great influence on the stability and integration degree of the subsequently formed semiconductor devices. Therefore, after the film layer is formed on the semiconductor substrate, it is necessary to planarize the uneven surface of the film layer. [0003] For example, a manufacturing process of a flash memory based on floating gate technology includes the...

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Problems solved by technology

[0006] The inventors found that, in the above chemical vapor deposition process, since the density of the isolation structure 101 in the storage area I and the peripheral area II is different, and it is higher than the surface of the floating gate oxide layer 102, the deposited floating gate polysilicon layer 103 is in the storage area. The junction area between I and peripheral region II has an undulating film surface (such as Figure 1A shown in 103a), and the chemical mechanical polishing process has a certain difference in the polishing rate of the storage area I and the peripheral area II, so finally the thickness of the remaining floating gate polysilicon layer 103 in the storage area I and the peripheral area II is different. There is a step difference between 103b

When the thickness of the remaining floating gate polysilicon layer 103 in the memory region I after chemical mechanical polishing meets the requirements, the thickness of the remaining floating gate polysilicon layer 103 in the peripheral region II will be too thin, and the floating gate polysilicon layer 103 in the peripheral region II will be too thin. It is easy to cause damage to the active area of ​​the underlying semiconductor substrate during removal, which in turn will cause the device to fail to open normally, and even cause the device to fail

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