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Systems and methods for sending data from non-volatile solid state devices before error correction

A non-volatile, error technique used in error detection/correction, digital transmission systems, response to error generation, etc.

Inactive Publication Date: 2017-08-18
HITACHI GLOBAL STORAGE TECH NETHERLANDS BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Therefore, sending blocks is delayed until the ECC algorithm is completed

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  • Systems and methods for sending data from non-volatile solid state devices before error correction
  • Systems and methods for sending data from non-volatile solid state devices before error correction
  • Systems and methods for sending data from non-volatile solid state devices before error correction

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Embodiment Construction

[0017] A system and method for transmitting data stored in non-volatile memory is provided. Once the data packet is retrieved from the non-volatile memory, it can be sent to the host before error correction is performed. Once all data packets for a block have been retrieved from non-volatile memory, error correction can be performed. If any data packets are retrieved with errors, they can be corrected and resent to the host.

[0018] figure 1 An exemplary system 100 implementing a communication protocol according to an embodiment of the disclosure is illustrated. System 100 includes host 102 in communication with target device 104 and storage 122 . Host 102 includes user applications 106, operating system 108, drivers 110, host memory 112, queues 118a, and communication protocols 114a. Target device 104 includes interface controller 117 , communication protocol 114 b , queue 118 b , and storage controller 120 in communication with storage volume 122 .

[0019] Host 102 ma...

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Abstract

Methods and systems for performing operations in a communications protocol are provided. A memory controller can retrieve data packets from the memory and send each retrieved data packet to a host, as each data packet is retrieved. The memory controller can retrieve an error correcting code (ECC) packet corresponding to the retrieved data packets and execute an ECC algorithm to identify and correct potential errors in the retrieved plurality of data packets. The memory controller can send any corrected data packets to the host if any of the retrieved data packets had errors and send a completion packet to the host.

Description

technical field [0001] The present disclosure relates to a system and method for transmitting data stored in a non-volatile solid-state device, and in particular to a system and method for transmitting data before error correction is complete. Background technique [0002] Non-volatile solid state devices (SSDs) are widely used for primary and secondary storage in computer systems. Some nonvolatile memories, such as phase change memory (PCM), resistive RAM (ReRAM), and magnetic RAM (MRAM), have bit error rates that are higher than those of dynamic read access memory (DRAM), But probably much lower than the bit error rate in NAND flash memory. Therefore, these moderate bit error rates require better error correction than the short Hamming codes used in DRAM. This can lead to long latencies when running the error correction algorithm. For example, implementing error-correcting codes (ECC, such as the full BCH code, from the acronyms of the code's inventors, Raj Bose, D.K. R...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/10
CPCG06F11/1044G06F11/1048G06F11/10H03M13/152G06F13/1668H04L1/0057
Inventor Z.Z.班迪克R.马蒂斯库M.秦D.武齐尼奇
Owner HITACHI GLOBAL STORAGE TECH NETHERLANDS BV