DDR SDRAM control circuit, DDR SDRAM chip, PCB and electronic equipment

Abstract

The invention relates to the technical field of integrated circuits, in particular to a DDR SDRAM control circuit, a DDR SDRAM chip, a PCB and electronic equipment. The DDR SDRAM control circuit comprises a delayed phase-locked loop, a clock circuit, a clock phase selector and a logic controller, wherein the delayed phase-locked loop is used for generating a preset clock signal; the clock circuit is used for generating a reference clock signal, the frequency of which is at least doubled; and the logic controller d for controlling a data strobe pulse DQS to be centrally aligned with a data pulse DQ according to the reference clock signal when a writing operation is carried out. Compared with the clock signal of the existing DDR SDRAM control circuit, the reference clock signal is a clock signal, the frequency of which is at least doubled, so that the low-frequency clock signals are replaced by high-frequency clock signals, the designers can decrease or shorten the length of high-speed clock wires connected to interface modules, and then benefit is brought to the balance the delayed control.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a DDR SDRAM control circuit, a DDR SDRAM chip, a PCB board and electronic equipment. Background technique [0002] In the application of SOC chip (System-on-a-Chip), for the double data rate synchronous dynamic random access memory (Double Data Rate SDRAM, DDR SDRAM) controller design, since the frequency of transmission data is as high as 400MHz, the clock frequency is 200MHz, In the read operation, and the data strobe (DQ Strobe, DQS) and the data pulse DQ (Data) are edge-aligned (Edge-Aligned), the DDR SDRAM controller needs to sample data and latch data in a short time to achieve 2 data samples are sampled in one clock cycle. However, during the write operation, due to the need for DQS and DQ center-aligned (Center-Aligned), the DDR SDRAM controller needs to combine clock edges with a difference of 1 / 4 clock cycle, and the existing technology adopts a relatively ...

AI Technical Summary

Problems solved by technology

[0004] An object of the embodiments of the present invention is to provide a DDR SDRAM control circuit, DDR SDRAM chip, PCB board and electronic equipment, which solves the low clock frequency and more clock connections of the read and write operations of the existing DDR SDRAM controller And complex, resulting in unbalanced technical problems

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