Novel 8TSRAM unit circuit system

Abstract

The invention belongs to the technical field of circuits and discloses a novel 8TSRAM unit circuit system. A circuit structure that a word line for reading data and a word line for writing data are respectively separated and a bit line for reading data and a bit line for writing data are respectively separated is adopted, and a self-locking data enabling pipe is inserted between an output end of a second phase inverter and an input end of a first phase inverter so as to control a write-data action. According to the novel 8TSRAM unit circuit system, the correct data writing is realized under a relatively low power supply voltage, so that the interference with stored data when the data is read is reduced, and the static noise allowance of a storage unit is increased.

Description

technical field [0001] The invention belongs to the field of circuit technology, in particular to a novel 8T SRAM unit circuit system. Background technique [0002] Random static memory (SRAM) is a very important part of the SoC system. Due to the reliability of read and write operations, the traditional 6-tube unit determines that its minimum operating voltage is difficult to continue to shrink as the manufacturing process advances. [0003] Traditional 6T SRAM storage unit: MP1, MN1 and MP2, MN2 two inverters form a latch, externally written data is stored in Q or QB, MN3, MN4 are switch tubes, WL is a word line, BL, BLB for the bit line. During write operation: If "0" is written to Q (the original state is "1"), first the bit lines BL and BLB are precharged to "1", and then BL and BLB are respectively set to "1" according to the type of data to be written. "0" and "1"; then set the word line WL to "1", so that the two switches MN3 and MN4 are turned on; the Q terminal c...

AI Technical Summary

Problems solved by technology

[0006] The traditional 6T SRAM storage unit, driven by the continuous reduction of power consumption requirements of SoC, as the minimum operating voltage gradually decreases, the voltage flip point of the inverter composed of MP1 and MN1 (or MP2, MN2) decreases, and the storage unit It is difficult to write data or write data fails, and as VDD drops, the static noise margin also drops, and the stability of the memory cell is threatened under low voltage conditions

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