High Speed ​​Clock Generation Circuit

Abstract

The present invention provides a high-speed clock generation circuit. The circuit comprise a control module and a loop oscillation module which are mutually connected, the control module is configured to determine that the period of conversion signals output by the loop oscillation module satisfies a preset period range or not according to the period relation between the conversion signals and crystal oscillation signals, regulate the period of delay control signals and the proportion relation of high-low level widths in the sampling signals when the period of conversion signals output by the loop oscillation module does not satisfy the preset period range and output the delay control signals and the sampling signals, and the loop oscillation module is configured to regulate the period of the conversion signals according to the period of the delay control signals in the low level period of the sampling signals, feed the output conversion signals back to the control module and satisfy that the conversion signals in the preset period range is clock signals to be solved. The high-speed clock generation circuit in the technical scheme is simple in structure and low in power consumption, can automatically regulate the internal delay to generate clock signals to be solved satisfying the preset period range so as to obtain continuously generated high-speed clock signals.

Description

technical field [0001] The present application relates to the field of circuit technology, in particular to a high-speed clock generation circuit. Background technique [0002] At present, the analog-to-digital conversion circuit in the electronic test instrument needs a conversion clock to control the conversion time during the analog-to-digital conversion process. Usually, when the required conversion clock is much higher than the crystal oscillator clock of the system, it is necessary to obtain a high-speed clock signal through a phase-locked loop circuit to ensure the realization of analog-to-digital conversion. However, due to the complex structure and high power consumption of the phase-locked loop circuit, a low-power clock technology is urgently needed to obtain a high-speed clock in a circuit requiring low power consumption. [0003] Currently, existing low-power techniques use the output of a latched comparator to trigger high-speed clock generation. figure 1 It ...

AI Technical Summary

Problems solved by technology

[0005] This application provides a high-speed clock generation circuit to solve the problems in the prior art that errors may occur and high-speed clocks cannot be obtained when using the output of a latch comparator to generate a high-speed clock

Images