Self-aligned gate contact

Abstract

A method of forming one or more self-aligned gate contacts (560) in a semiconductor device includes providing a substrate (100) having formed thereon at least one gate stack (520), where the gate stack includes a gate dielectric (420) and a gate electrode (550) formed over an active region in or on the substrate (100), and where the substrate further has formed thereon a spacer material (320) coating lateral sides of the at least one gate stack (520). The method additionally includes selectively recessing the gate electrode (550) of the at least one gate stack (520) against the spacer material (320), thereby creating a first set of recess cavities. The method additionally includes filling the first set of recess cavities with a dielectric material gate cap (340). The method additionally includes etching at least one via above the at least one gate stack (520) and through the dielectric material gate cap (340), where etching the at least one via (920) comprises selectively etching against the spacer material, thereby exposing the gate electrode (550). The method further includes forming, in the at least one via (920), a gate contact (560) electrically connecting the gate electrode (550).

Description

technical field [0001] The present invention relates to the field of semiconductor devices, and more particularly to methods of forming gate contacts of transistors in such devices. Background technique [0002] In the manufacture of semiconductor circuits, and more precisely at the back end of the pipeline stages of the manufacturing process, it is necessary to form gate contacts connected to their corresponding contact lines. Unlike source and drain contacts, the area available for these gate contacts on the device channel is very limited. Furthermore, minimum area rules limit how small these gate contacts can be made. Thus, forming a gate contact on top of the device channel results in disturbances in the form of shadowing and shorting of adjacent gate, source, and drain contacts, with attendant implications for preventing small Offset's incompetence, which further exacerbates the problem. [0003] From figure 1 As can be seen in , the result is that gate contacts can...

AI Technical Summary

Problems solved by technology

These strict circuit design rules greatly limit the flexibility of cell routing; a problem that becomes increasingly relevant as scaling advances

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