EMI protection chip packaging structure and packaging method

A chip packaging structure and chip packaging technology, applied in electrical components, electric solid devices, circuits, etc., can solve problems such as cracking of chip packaging structures, achieve the effects of improving bonding strength, reducing costs, and avoiding curling

Pending Publication Date: 2017-10-13
SJ SEMICON JIANGYIN CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0012] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a chip packaging structure and packaging met

Method used

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  • EMI protection chip packaging structure and packaging method
  • EMI protection chip packaging structure and packaging method
  • EMI protection chip packaging structure and packaging method

Examples

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Example Embodiment

[0050] Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

[0051] see Figure 2 to Figure 10. It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of ​​the present invention, so that only the components related to the present invention are shown in the diagrams rather than the number, shape and Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the...

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Abstract

The invention provides an EMI protection chip packaging structure and an EMI protection chip packaging method. The structure comprises a rewiring layer comprising a first plane and a second plane opposite to each other; a metal lug formed on the first plane of the rewiring layer; a semiconductor chip electrically connected with the second plane of the rewiring layer; an electromagnetic shielding frame formed on the second plane of the rewiring layer and arranged around the semiconductor chip; packaging material covered on the semiconductor chip and the electromagnetic shielding frame, wherein he surface of the packaging material is exposed out of the electromagnetic shielding frame; and an electromagnetic shielding layer formed on the surface of the packaging material. According to the packaging structure provided by the invention, the fan-out type packaging structure is used for achieving electromagnetic shielded packaging, the used packaging material is the same as or similar to the material of the rewiring layer, so that CTE mismatch therebetween is lowered, and crack probability is reduced; the packaging structure has relatively high integration level, better packaging performance, and wide application prospects in the field of semiconductor packaging.

Description

technical field [0001] The invention relates to a semiconductor package structure and a package method, in particular to a chip package structure and a package method for EMI protection. Background technique [0002] With the increasingly powerful functions of integrated circuits, higher performance and higher integration, and the emergence of new integrated circuits, packaging technology plays an increasingly important role in integrated circuit products, and in the value of the entire electronic system The proportion is increasing. At the same time, as the feature size of integrated circuits reaches the nanometer level, transistors are developing towards higher density and higher clock frequency, and packaging is also developing towards higher density. [0003] Due to the advantages of miniaturization, low cost and high integration, as well as better performance and higher energy efficiency, fan-out wafer-level packaging (fowlp) technology has become a An important packa...

Claims

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Application Information

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IPC IPC(8): H01L23/552H01L23/31
CPCH01L23/552H01L23/3107H01L2224/96H01L2224/12105H01L2224/04105H01L2924/3025
Inventor 陈彦亨林正忠
Owner SJ SEMICON JIANGYIN CORP
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