Simulation method for improving PCIE eye diagram margin

Abstract

The invention relates to the field of PCIE design, in particular to a simulation method for improving PCIE eye diagram margin. According to the simulation method, TX Vswing is reduced by adjusting TX-end setting (Pre-cursor, Cursor, Post-cursor), accordingly the link crosstalk is decreased to ensure the integrity of designed system link signals. By adopting the simulation method, the space waste brought by link design optimization is avoided, and increase of the design time and cost is avoided. The simulation method is simple, efficient and easy to achieve.

Description

technical field [0001] The invention relates to the field of PCIE design, in particular to a simulation method for improving the PCIE eye diagram margin. The simulation method reduces the TX Vswing by adjusting the settings of the TX end (Pre-cursor, Cursor, Post-cursor), thereby reducing the link crosstalk, so as to ensure the integrity of the designed system link signal. This simulation method avoids the waste of space brought about by the optimized link design, avoids the increase of design time and cost, and is simple, efficient and easy to implement. Background technique [0002] In the design of server motherboards, PCIE (peripheral component interconnect express, a high-speed serial computer expansion bus standard) often has short wiring lengths, excessive crosstalk, and discontinuous impedance. This situation will cause the signal to be affected by crosstalk and reflection, and the integrity of the signal will be reduced. [0003] In view of the short length of the...

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Problems solved by technology

[0002] In the design of server motherboards, PCIE (peripheral component interconnect express, a high-speed serial computer expansion bus standard) often has short wiring lengths, excessive crosstalk, and discontinuous impedance.

This situation will cause the signal to be affected by crosstalk and reflection, and the integrity of the signal will be reduced

[0003] In view of the short length of the bus line, excessive crosstalk, discontinuous impedance, etc., usually the designer will try to optimize the design, increase the space of the line to avoid crosstalk, and the length of the line to avoid too serious signal reflection. However, if the wiring space and winding space are increased, the size of the board will increase. In actual situations, there is generally not enough space or time to optimize the design.

Therefore, this situation inevitably increases the time required for design and increases the design cost.

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