Simulation method for improving PCIE eye diagram margin

A simulation method and margin technology, applied in design optimization/simulation, special data processing applications, instruments, etc., can solve problems such as increased design cost, large crosstalk, and excessive crosstalk, so as to ensure integrity and reduce link Effect of Crosstalk Size

Inactive Publication Date: 2017-10-20
ZHENGZHOU YUNHAI INFORMATION TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] In the design of server motherboards, PCIE (peripheral component interconnect express, a high-speed serial computer expansion bus standard) often has short wiring lengths, excessive crosstalk, and discontinuous impedance.
This situation will cause the signal to be affected by crosstalk and reflection, and the integrity of the signal will be reduced
[0003] In view of the short length of the bus line, excessive crosstalk, discontinuous impedance, etc., usu

Method used

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  • Simulation method for improving PCIE eye diagram margin
  • Simulation method for improving PCIE eye diagram margin

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0017] The simulation method of the present invention will be further described in detail in conjunction with specific embodiments below:

[0018] Through the simulation analysis of the link with short PCIE bus trace and large crosstalk on the main board, the judgment standard is that the margin must be greater than 9, and only when it is greater than 9 can the link signal integrity be guaranteed.

[0019] Among them, the TX end sets (Pre-cursor, Cursor, Post-cursor) sum 0x3F(63). Under this amplitude, even if preset0-9 traverses, the eye diagram (the eye diagram refers to the use of experimental methods to estimate and improve system performance) An observed graphic) margin is not ideal (High, low, right, and left represent the eye margin), the test results take (0x0b, 0x29, 0x0b) as an example, and the specific results are shown in Table 1.

[0020] Lane

Pre-cursor

Cursor

Post-cursor

High

Low

Right

Left

RxCtle

0

0x0b

0x2...

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Abstract

The invention relates to the field of PCIE design, in particular to a simulation method for improving PCIE eye diagram margin. According to the simulation method, TX Vswing is reduced by adjusting TX-end setting (Pre-cursor, Cursor, Post-cursor), accordingly the link crosstalk is decreased to ensure the integrity of designed system link signals. By adopting the simulation method, the space waste brought by link design optimization is avoided, and increase of the design time and cost is avoided. The simulation method is simple, efficient and easy to achieve.

Description

technical field [0001] The invention relates to the field of PCIE design, in particular to a simulation method for improving the PCIE eye diagram margin. The simulation method reduces the TX Vswing by adjusting the settings of the TX end (Pre-cursor, Cursor, Post-cursor), thereby reducing the link crosstalk, so as to ensure the integrity of the designed system link signal. This simulation method avoids the waste of space brought about by the optimized link design, avoids the increase of design time and cost, and is simple, efficient and easy to implement. Background technique [0002] In the design of server motherboards, PCIE (peripheral component interconnect express, a high-speed serial computer expansion bus standard) often has short wiring lengths, excessive crosstalk, and discontinuous impedance. This situation will cause the signal to be affected by crosstalk and reflection, and the integrity of the signal will be reduced. [0003] In view of the short length of the...

Claims

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Application Information

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IPC IPC(8): G06F17/50
CPCG06F30/20
Inventor 李永翠
Owner ZHENGZHOU YUNHAI INFORMATION TECH CO LTD
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