Verification method and verification system for interface controller

An interface controller and controller technology, applied in the field of interface controller verification method and verification system, can solve the problems of increasing verification workload and so on

Active Publication Date: 2017-11-10
北京东土军悦科技有限公司 +1
View PDF4 Cites 10 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When designing the SOC chip, it is necessary to verify the three built-in interface controllers. However, because different interfaces follow different protocols, when verifying the interface controller, it is necessary to verify the interface

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Verification method and verification system for interface controller
  • Verification method and verification system for interface controller
  • Verification method and verification system for interface controller

Examples

Experimental program
Comparison scheme
Effect test

Example Embodiment

[0042] Example one

[0043] Such as Figure 2a Shown is a schematic structural diagram of a verification system for an interface controller provided by Embodiment 1 of the present invention, including: a test platform 1 and at least one mirror controller 2i (i is between 1 and n), each mirror controller 2i It is configured according to the type of interface controller 3i included in the chip under test 3, and the mirror controller 2i is connected to the interface controller 3i of the same type, and the mirror controller is also connected to the test platform 1, wherein:

[0044] The test platform 1 is used to generate initial test data when verifying any interface controller 3i (i is between 1 and n) in the tested chip 3, and use simple The driver sends to the mirror controller 2i corresponding to the interface controller 3i; and receives the fourth test data returned by the mirror controller 2i; compares the initial test data with the fourth test data; and according to the compari...

Example Embodiment

[0082] Example two

[0083] Such as Figure 5 As shown, it is a schematic flowchart of a verification method for a test platform-side interface controller provided in the second embodiment of the present invention, which may include the following steps:

[0084] S11. Generate initial test data when verifying any interface controller in the tested chip.

[0085] S12. Send the initial test data to the mirror controller corresponding to the interface controller using a simple driver.

[0086] During specific implementation, when the initial test data is sent to the mirror controller, the mirror controller can be triggered to perform data format conversion on the received initial test data to obtain the first test data, and the The test data is sent to the mirror controller corresponding to the interface controller.

[0087] S13. Receive fourth test data returned by the mirror controller.

[0088] Wherein, the fourth test data is obtained by the mirror controller performing data format conv...

Example Embodiment

[0100] Example three

[0101] Such as Image 6 As shown, it is a schematic flowchart of a method for verifying a mirror controller-side interface controller provided in Embodiment 3 of the present invention, which may include the following steps:

[0102] S21: After receiving the initial test data sent by the test platform using a simple driver, perform data format conversion on the initial test data to obtain the first test data.

[0103] Wherein, the initial test data is generated when the test platform verifies any interface controller in the chip under test.

[0104] S22. Send the first test data to the chip under test.

[0105] S23. Receive third test data sent by the chip under test, and perform data format conversion processing on the third test data to obtain fourth test data.

[0106] Wherein, the third test data is obtained by performing data format conversion on the second test data by the chip under test again, and the second test data is obtained by performing the data forma...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention discloses a verification method and a verification system for an interface controller. The method comprises the steps of when any interface controller in a chip to be tested is verified, sending generated initial test data to a mirror image controller corresponding to the interface controller by using a simple drive program, triggering the mirror image controller to perform data format conversion on the initial test data to acquire first test data, and sending the first test data to the tested chip; receiving fourth test data returned by the mirror image controller, wherein the fourth test data is acquired through performing data format conversion on third test data by the mirror image controller, and the third test data is acquired through further performing data format conversion on second test data by the interface controller in the tested chip; comparing the initial test data with the fourth test data; and determining a verification result of the interface controller according to a comparison result. Therefore, the interface controllers with different protocols can be verified by using the data with simple protocols.

Description

Technical field [0001] The present invention relates to the field of data communication technology, in particular to a verification method and a verification system of an interface controller. Background technique [0002] In the process of chip design, multiple interfaces are usually configured for the chip. Take SOC (System On Chip, system on chip) as an example. figure 1 As shown, the SOC chip is provided with UART Controller (Universal Asynchronous Receiver / Transmitter Controller), SPI (Serial Peripheral Interface Controller) and I2C (Inter-Integrated Circuit Controller). , Inter-Integrated Circuit Interface Controller). When designing the SOC chip, it is necessary to verify the three built-in interface controllers. However, because different interfaces follow different protocols, when verifying the interface controller, it needs to be verified according to the interface protocol. The controller performs verification, that is, different driver programs and monitor programs n...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): G06F11/26
CPCG06F11/26
Inventor 刘多一
Owner 北京东土军悦科技有限公司
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products