Reconfiguration method of vlsi array driven by point of failure
A technology for array reconfiguration and point of failure, applied in instrumentation, calculation, electrical digital data processing, etc., can solve problems such as low reconfiguration speed, and achieve the effect of efficient and fast reconfiguration and fast array reconfiguration
Active Publication Date: 2020-07-21
GUANGDONG UNIV OF TECH
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Since the number of faulty PEs in practical applications is very small, the number of available PEs is almost the same as the size of the original array, and the reconstruction of the array by accessing all available PEs will inevitably lead to a slow reconstruction speed
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[0018] Hereinafter, the present invention will be further described in detail with reference to the examples and drawings, but the implementation of the present invention is not limited thereto.
[0019] The present invention aims at the common phenomenon of extremely low failure rate in practical applications, and proposes a real-time, high-efficiency and rapid reconstruction technology of the array when a failure occurs. Specific operations such as figure 1 Shown. Such as figure 1 As shown in (a), the size of the physical array is 4×8, and the number of FPEs is 4. For ease of presentation, number all PEs in the array, such as e 1,1 The number is 1 in the array, and PE 1 will be used later to represent this PE. The physical columns in the array are represented as C from left to right 1 ,C 2 ,...,C 8 The specific steps of the algorithm are as follows.
[0020] 1. First of all, from Definition 1, LA[C 1 ,C 8 ]=A[C 1 ,C 6 ), the LA[C 1 ,C 8 ] Move to the last physical column C ...
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The invention discloses a fault point driven VLSI (very large scale integrated) array reconfiguration method. The method includes: finding out left-most areas LA (C1, Cn) of a whole array A, then performing shift operation to move each FPE (Faulty Processing Element) in one left-most area to the last physical column in the left-most area, and performing shift operation to move each FPE in another left-most area to the last physical column in the left-most area till each FPE in the last left-most area is moved to the last physical column in the last left-most area, in other words, the right margin of the current lest-most area is Cn. From a few number of fault processors and the locations thereof, the fault processors in the array can be moved to the same logical column as much as possible by only performing shift operation on the few fault processors in the array, the original array structure is maintained to the uttermost degree, and further efficient rapid reconfiguration of the logical array is realized.
Description
Technical field [0001] The invention relates to a VLSI array reconstruction method, in particular to an efficient and fast VLSI array reconstruction method. Background technique [0002] The grid topology is widely used in Very Large Scale Integrated (VLSI) systems and multi-core systems because of its simple structure, easy expansion, regular structure and easy realization. With the development of semiconductor technology, hundreds of processing elements (PEs) can be integrated on a single chip. However, with the rapid increase in chip integration density, the possibility of PEs failure during manufacturing and processing also increases. These Faulty Processing Elements (FPEs) will affect the stability and reliability of the entire system. Therefore, for arrays with FPEs, fast and effective fault-tolerant technology is required to improve the stability and reliability of the system. [0003] Summarizing the related research work in recent years, almost all reconstruction algori...
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IPC IPC(8): G06F30/392G06F115/06
CPCG06F30/392G06F2115/06
Inventor 吴亚兰武继刚姜文超王勇
Owner GUANGDONG UNIV OF TECH