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Thin-film transistor array, image display device, and method for manufacturing thin-film transistor array

A technology of thin-film transistors and arrays, which is applied in the manufacturing fields of thin-film transistor arrays, image display devices, and thin-film transistor arrays. It can solve the problems of low patterning yield, short circuit of gate wiring and capacitor wiring, etc., to prevent damage and realize low-temperature process Effect

Active Publication Date: 2017-11-28
TOPPAN HLDG INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, printing has lower patterning yields than photolithography, so short circuits may occur between gate wiring and capacitor wiring.

Method used

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  • Thin-film transistor array, image display device, and method for manufacturing thin-film transistor array
  • Thin-film transistor array, image display device, and method for manufacturing thin-film transistor array
  • Thin-film transistor array, image display device, and method for manufacturing thin-film transistor array

Examples

Experimental program
Comparison scheme
Effect test

no. 1 approach

[0054] figure 1 The thin film transistor array 100 according to the first embodiment is shown in . The thin film transistor array 100 has: an insulating substrate 1; a plurality of gate electrodes 2 formed on the insulating substrate 1, a plurality of gate wirings 2' connected to the gate electrodes 2, a plurality of capacitor electrodes 10, and A plurality of capacitor wirings 10'; a gate insulating film 3 formed on the insulating substrate 1, a gate electrode 2, a gate wiring 2', a capacitor electrode 10, and a capacitor wiring 10'; a plurality of capacitors formed on the gate insulating film 3 A source electrode 4, a plurality of source wiring 4' connected to the source electrode 4, a plurality of drain electrodes 5, and a plurality of pixel electrodes 7 connected to the drain electrode 5, the pixel electrode 7 and the capacitor electrode via the gate insulating film 3 10 overlapping to have a storage capacitor, the source electrode 4 and the drain electrode 5 overlap the ...

no. 2 approach

[0070] Figure 4 A thin film transistor array 200 according to the second embodiment is shown in . The thin film transistor array 200 has: an insulating substrate 1; a plurality of gate electrodes 2 formed on the insulating substrate 1, a plurality of gate wirings 2' connected to the gate electrodes 2, a plurality of capacitor electrodes 10, and A plurality of capacitor wirings 10'; a gate insulating film 3 formed on the insulating substrate 1, a gate electrode 2, a gate wiring 2', a capacitor electrode 10, and a capacitor wiring 10'; a plurality of capacitors formed on the gate insulating film 3 A source electrode 4, a plurality of source wiring 4' connected to the source electrode 4, a plurality of drain electrodes 5, and a plurality of pixel electrodes 7 connected to the drain electrode 5, the pixel electrode 7 and the capacitor electrode via the gate insulating film 3 10 overlapping to have a storage capacitor, the source electrode 4 and the drain electrode 5 overlap the ...

Embodiment 1

[0097] Specific examples will be described. As Example 1, using Figure 3A ~ Figure 3G The process shown produces Figure 2A The thin film transistor array 100 is shown. First, a glass substrate was prepared as an insulating substrate 1, Ag ink was offset-printed and sintered to form a gate electrode 2, a gate wiring 2', a capacitor electrode 10, and a capacitor wiring 10' ( Figure 3A ).

[0098] Next, the polyvinylphenol solution was die coated and fired to form the gate insulating film 3 ( Figure 3B ).

[0099] Then, Ag ink is carried out offset printing and sintering, has formed source electrode 4, source electrode wiring 4 ', drain electrode 5 and pixel electrode 7 ( Figure 3C ). Next, the polythiophene organic semiconductor solution was flexographically printed and sintered to form a semiconductor layer 6 ( Figure 3D ). Then, the fluororesin solution is screen-printed and sintered to form a protective layer 6' ( Figure 3E ).

[0100] Next, a 10 kΩ chip resi...

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Abstract

Provided are a thin-film transistor array and a method for manufacturing the same, whereby failure of a gate driver or a power source can be prevented even when a short circuit occurs between gate wirings / capacitor wirings. The thin-film transistor array according to the present invention is provided with: an insulated substrate; a gate insulation film; and, sandwiching the gate insulation film therebetween, a gate electrode, gate wiring connected to the gate electrode, a capacitor electrode, and capacitor wiring connected to the capacitor electrode, and a source electrode, source wiring connected to the source electrode, a drain electrode, and a pixel electrode connected to the drain electrode; the pixel electrode being superposed on the capacitor electrode via the gate insulation film and having a storage capacitance, the source electrode and the drain electrode being superposed on the gate electrode via the gate insulation film, and the thin-film transistor array having a semiconductor layer between the source electrode and the drain electrode and having a resistance partway along the capacitor wiring.

Description

technical field [0001] The invention relates to a thin film transistor array, an image display device and a manufacturing method thereof. Background technique [0002] Thin film transistor arrays have been developed, and liquid crystal display devices or electrophoretic display devices using thin film transistor arrays have been developed. Conventionally, photolithography is used for patterning electrodes of a thin film transistor array. [0003] In recent years, thin-film transistor arrays obtained by printing have attracted attention as cheaper thin-film transistor arrays, or thin-film transistor arrays that can realize low-temperature processes and are suitable for plastic substrates (Patent Document 1). [0004] However, since printing has lower patterning yields than photolithography, short circuits may occur between gate wiring and capacitor wiring. [0005] prior art literature [0006] patent documents [0007] Patent Document 1: Japanese Patent Laid-Open No. 200...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G02F1/1343G02F1/1368G09F9/30H01L21/822H01L27/04H01L29/786
CPCG09F9/30H01L21/822H01L27/04G02F1/136204H01L27/1255H01L27/1292G02F1/1343H01L27/1222H01L29/786G02F1/1362G09F9/35
Inventor 石崎守
Owner TOPPAN HLDG INC
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