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Module-level and SoC-level reusable verification system and verification method

A verification system and module-level technology, applied in the field of verification systems, can solve the problems of increasing the complexity of chip design and application scenarios, and achieve the effects of shortening construction time, improving verification efficiency, and facilitating optimization and management.

Inactive Publication Date: 2017-12-01
SHANDONG SINOCHIP SEMICON
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AI Technical Summary

Problems solved by technology

[0002] With the development of SoC (System on Chip, system on chip) technology, more and more modules are packaged on a chip, such as CPU (Central Processor Unit), memory, clock circuit, peripheral equipment and various interfaces, etc., SoC Technology has improved the reliability of system design, but it has greatly increased the complexity of chip design and application scenarios, and puts forward higher requirements for logic function verification and chip-level verification of chip functional modules.

Method used

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  • Module-level and SoC-level reusable verification system and verification method
  • Module-level and SoC-level reusable verification system and verification method
  • Module-level and SoC-level reusable verification system and verification method

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Embodiment Construction

[0014] Below in conjunction with accompanying drawing, the present invention is described in further detail:

[0015] Such as figure 1 As shown, a module-level and SoC-level reusable verification system of the present invention integrates the traditional module-level verification platform and SoC-level verification platform into a verification platform, uses scripts and template libraries to generate a general verification framework, and generates Add reusable verification components to the verification architecture, and add corresponding test stimuli according to the different stages of module-level verification or SoC-level verification. Module-level test stimuli are generally written in verification languages, and system-level test stimuli are generally written in C language. Complete the construction of module-level and SoC-level verification platforms. In this verification platform, except for test stimulus, other components can be reused in module-level verification and...

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Abstract

The present invention discloses a module-level and SoC-level reusable verification system. The system comprises: a test excitation unit connected with an ENV unit; the ENV unit comprises a generator module, a proxy module, and driver module that drives the DUT configuration interface that are sequentially connected with the test excitation unit and are openable and closable; the ENV unit further comprises two monitors for monitoring the DUT configuration interface, a Golden Model unit for generating the reference output, and a scoreboard for data comparison; the two monitors are respectively connected with the Golden Model unit and the scoreboard; and the Golden Model unit is connected with the scoreboard. Beneficial effects of the technical scheme of the present invention are that: problems of the non-reusable code and low verification efficiency caused by a respective set of verification platforms at the module-level and the SoC-level in the traditional verification platform are solved, integration of the module-level verification platform and the software and hardware co-verification platform is realized, the optimization and management of the verification platform are facilitated, the verification platform setup time is greatly shortened, and the verification efficiency is improved.

Description

technical field [0001] The invention relates to a reusable verification system at module level and SoC level. Background technique [0002] With the development of SoC (System on Chip, system on chip) technology, more and more modules are packaged on a chip, such as CPU (Central Processor Unit), memory, clock circuit, peripheral equipment and various interfaces, etc., SoC Technology has improved the reliability of system design, but it has greatly increased the complexity of chip design and application scenarios, and puts forward higher requirements for logic function verification and chip-level verification of chip functional modules. According to statistics, for a logically complex chip development, 60%~70% of the entire product cycle needs to be spent on chip verification, and chip verification has become the key to successful chip development and timely listing. How to cover chip functions more efficiently, discover chip logic function errors, and realize SoC chip softw...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
CPCG06F30/398G06F2117/08
Inventor 李文军李风志戴绍新姚香君石易明
Owner SHANDONG SINOCHIP SEMICON
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