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A multi-chip integrated packaging method

A packaging method and multi-chip technology, applied in the manufacturing of electrical components, circuits, semiconductor/solid-state devices, etc., can solve the problems of long trial production cycle, high design cost, and inability to meet time requirements, so as to reduce design costs and reduce costs. The effect of design link and shortening production cycle

Active Publication Date: 2019-09-24
池州华宇电子科技股份有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] At present, the market has higher and higher requirements for the diversification of functions of packaging products and the functions of a single chip. In order to realize such requirements of customers, design companies need to redesign the original chip so that a single chip has multiple functions, which not only reduces the design cost High, the cycle from design to trial production is too long, and needs to be continuously optimized, which cannot meet the time requirements of rapid development and change

Method used

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  • A multi-chip integrated packaging method

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Experimental program
Comparison scheme
Effect test

Embodiment 1

[0017] Such as figure 1 Shown, a kind of multi-chip integrated packaging method, this method comprises the following steps:

[0018] 1) Chip layout: according to the function and size of multiple functional chips, the chip layout method is determined, and the chip layout method is one or more combinations of horizontal layout in the horizontal direction and stacking layout in the vertical direction;

[0019] 2) Loading and curing: According to the chip arrangement method selected in step 1), each functional chip is loaded in sequence until all the functional chips are loaded and sent to an oven for baking and curing. The drying temperature of the oven is 175 ℃, the drying time is 2.5h;

[0020] 3) Wiring: Place the functional chip after loading and curing in step 2) on the upper end of the bonding heating platform, and automatically plant the ball on the functional chip. Make a reverse slicing platform on the top surface, and use bonding wire to interconnect the reverse slic...

Embodiment 2

[0027] Such as figure 1 Shown, a kind of multi-chip integrated packaging method, this method comprises the following steps:

[0028] 1) Chip layout: according to the function and size of multiple functional chips, the chip layout method is determined, and the chip layout method is one or more combinations of horizontal layout in the horizontal direction and stacking layout in the vertical direction;

[0029] 2) Loading and curing: According to the chip arrangement method selected in step 1), each functional chip is loaded in sequence until all the functional chips are loaded and sent to an oven for baking and curing. The drying temperature of the oven is 173 ℃, the drying time is 2.5h;

[0030] 3) Wiring: Place the functional chip after loading and curing in step 2) on the upper end of the bonding heating platform, and automatically plant the ball on the functional chip. Make a reverse slicing platform on the top surface, and use bonding wire to interconnect the reverse slic...

Embodiment 3

[0037] Such as figure 1 Shown, a kind of multi-chip integrated packaging method, this method comprises the following steps:

[0038] 1) Chip layout: according to the function and size of multiple functional chips, the chip layout method is determined, and the chip layout method is one or more combinations of horizontal layout in the horizontal direction and stacking layout in the vertical direction;

[0039] 2) Loading and curing: According to the chip arrangement method selected in step 1), each functional chip is loaded in turn until all the functional chips are loaded and sent to an oven for baking and curing. The drying temperature of the oven is 174 ℃, the drying time is 2.5h;

[0040] 3) Wiring: Place the functional chip after loading and curing in step 2) on the upper end of the bonding heating platform, and automatically plant the ball on the functional chip. Make a reverse slicing platform on the top surface, and use bonding wire to interconnect the reverse slicing ...

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Abstract

The invention discloses a method for integrating and packing multiple chips. The method includes the following 7 steps: arranging chips, performing mounting and curing, performing wiring, performing plastic packaging, electroplating, trimming and forming, and packaging. The method can assembly chips having different functions, and packages the chips into a single chip, meets requirements of different clients at the maximum level within short time, reduces designing, increases the integration of the single chip, shortens production cycle, and lowers designing cost.

Description

technical field [0001] The invention relates to the field of chip packaging, in particular to a multi-chip integrated packaging method. Background technique [0002] At present, the market has higher and higher requirements for the diversification of functions of packaging products and the functions of a single chip. To realize such requirements of customers, design companies need to redesign the original chip so that a single chip has multiple functions, which not only reduces the design cost High, the cycle from design to trial production is too long, and needs to be continuously optimized, which cannot meet the time requirements of rapid development and change. In view of the above defects, it is necessary to design a multi-chip integrated packaging method. Contents of the invention [0003] The purpose of the present invention is to provide a multi-chip integrated packaging method, which can integrate and package multiple functional chips, and has a short production c...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/56
CPCH01L21/56
Inventor 彭勇李宏图谢兵赵从寿张友位王明辉
Owner 池州华宇电子科技股份有限公司
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