Simulate Multiport Memory Element Circuits
A technology of memory elements and memory circuits, applied in static memory, digital memory information, information storage, etc., to solve problems such as limiting overall bandwidth and speed
Active Publication Date: 2022-02-11
INTEL CORP
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Problems solved by technology
This limits the overall bandwidth and speed at which the integrated circuit can perform memory access operations
[0004] Certain operations of integrated circuits require relatively high memory access bandwidth and speed capabilities, which cannot be easily achieved using dual-port memory elements
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Embodiment Construction
[0016] Embodiments of the invention relate to integrated circuit memory elements having multiple ports. A memory element, also sometimes referred to as a cell, may contain any suitable number of transistors.
[0017] The memory elements may be used in any suitable integrated circuit using memory. These integrated circuits may be memory chips, digital signal processing circuits with memory arrays, microprocessors, application specific integrated circuits with memory arrays, programmable logic devices such as programmable logic device integrated circuits in which memory elements are used to configure the memory integrated circuit or any other suitable integrated circuit. Programmable integrated circuits on which memory elements are used may include, for example, programmable array logic (PAL), programmable logic array (PLA), field programmable logic array (FPLA), electrically programmable logic device (EPLD), electrically programmable Erasable Programmable Logic Devices (EEPLD...
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The present invention relates to simulating multi-port memory element circuits. An integrated circuit may include a circuit of memory elements. The memory element circuit may include a plurality of dual-port memory elements controlled to effectively form a multi-port memory element having a plurality of read and write ports. Individual groups of dual-port memory elements can be coupled to each write port. Write data may be received in parallel through one or more of the write ports and stored on the banks. Switching circuitry may be coupled between the bank of memory element circuitry and the read port. The switching circuit may be controlled using a read control signal generated by a logical XOR based control circuit. The control circuit may include a dual-port memory element that stores addressing signals associated with writing data. The read control signal may control the switching circuitry to selectively route the most recently written data to the corresponding read port during a data read operation.
Description
[0001] This application claims priority to US Patent Application No. 15 / 174,460, filed June 6, 2016, which is hereby incorporated by reference in its entirety. Background technique [0002] Integrated circuits often contain memory elements. Memory elements can be used to store data. Memory elements are often arranged in arrays. In a typical array, data lines are used to write data into memory elements and data lines are used to read data from memory elements loaded with data. [0003] The memory elements can be configured in a dual port arrangement. Conventional dual-port memory elements store data received through the write port. Data is read from the dual port memory element through the read port. Such dual-port memory elements support only a single write or read operation at a given time. This limits the overall bandwidth and speed with which the integrated circuit can perform memory access operations. [0004] Certain operations of integrated circuits require relativ...
Claims
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IPC IPC(8): G11C7/10
CPCG11C7/1075G11C8/12G11C8/16G06F5/00G06F9/30141G11C8/00
Inventor P.R.朱
Owner INTEL CORP