A kind of manufacturing method of 3D NAND flash memory

Abstract

The present invention provides a method for manufacturing 3D NAND flash memory. The manufacturing method of the present invention includes the following steps: providing a device wafer with epitaxial growth; providing a connection wafer without epitaxial growth; connecting the device wafer with at least one of the The connection wafers mentioned above are connected as a whole. The stack connection between the wafers is realized by preparing two different types of wafers, the device wafer and the connection wafer, which overcomes the layer limit of the current channel preparation process for the O / N stack structure; and because only the device Wafers need to undergo epitaxial growth and polysilicon deposition steps connecting silicon epitaxial growth and polysilicon layer in the channel sidewall stack structure, and connecting wafers saves the process steps of epitaxial growth and polysilicon deposition, which simplifies the process and improves efficiency; Through the process of the present invention, the limitation of the number of layers of the O / N stack structure can be broken through with low cost and high efficiency, thereby improving the overall performance of the 3D NAND flash memory.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a 3D NAND flash memory structure and a manufacturing method thereof, in particular to a 3D NAND manufacturing method capable of increasing channel depth. Background technique [0002] With the development of planar flash memory, the production process of semiconductors has made great progress. However, in recent years, the development of planar flash memory has encountered various challenges: physical limits, existing development technology limits, and storage electron density limits. In this context, in order to solve the difficulties encountered in planar flash memory and to seek lower production costs per unit storage unit, various three-dimensional (3D) flash memory structures have emerged, such as 3D NOR (3D or not) flash memory and 3D NAND (3D NAND) flash memory. [0003] Wherein, in the 3D flash memory of the NOR structure, memory cells are arranged in parallel...

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Problems solved by technology

[0018] However, in the above process, as the number of stacked O / N (Oxide / Nitride) stack structures in 3D NAND flash memory increases, it becomes more and more difficult to form through-etched channels in three-dimensional memories. The channel etching process can support less than 73 pairs of O / N (Oxide / Nitride) stacks, although there are channel etching processes that support more than 73 pairs of O / N (Oxide / Nitride) stacks, but this process The cost is very expensive, which seriously restricts the development of 3D NAND flash memory technology

Not only that, in the above process steps, the realization of silicon epitaxial growth in the channel, silicon and oxide deposition, ion implantation and other processes also increases with the increasing number of O / N (Oxide / Nitride) layers. become more and more difficult

These problems will affect the preparation of the channel and the performance of the final 3D NAND flash memory

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