Method for manufacturing 3D NAND flash memory with large number of stacked layers and 3D NAND flash memory

Abstract

The present invention provides a method for manufacturing a 3D NAND flash memory with a large number of stacked layers and a 3D NAND flash memory. The method comprises a step of providing a substratewafer with a MOS device region and a first memory device region thereon, a step of providing a bonding wafer with a metal wiring region and a second memory device region, a step of performing bondingconnection specifically comprises the steps of overturning the bonding wafer such that the metal wiring region is corresponding to the MOS device region and the second memory device region is corresponding to the first memory device region and performing direct bonding connection of the bonding wafer and the substrate wafer by Van der Waals force, a step of processing after connection including the steps of performing substrate thinning on the bonding wafer, manufacturing a metal interconnection layer and forming a metal connection line of a MOS device and a storage device. According to the invention, the limitation of the number of layers of an N / O stack structure by an existing process is overcome, the 3D NAND flash memory with the large number of stacked layers is obtained, and the storage capacity of the 3D NAND flash memory is improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a 3D NAND flash memory structure and a manufacturing method thereof, in particular to a manufacturing method of a high-stacked 3D NAND flash memory. Background technique [0002] With the development of planar flash memory, the production process of semiconductors has made great progress. However, in recent years, the development of planar flash memory has encountered various challenges: physical limits, existing development technology limits, and storage electron density limits. In this context, in order to solve the difficulties encountered in planar flash memory and to seek lower production costs per unit storage unit, various three-dimensional (3D) flash memory structures have emerged, such as 3D NOR (3D or not) flash memory and 3D NAND (3D NAND) flash memory. [0003] Wherein, in the 3D flash memory of the NOR structure, memory cells are arranged in parallel betw...

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Problems solved by technology

[0018] However, in the above process, in order to obtain a larger storage capacity per unit chip area, the number of O / N (Oxide / Nitride) stacked structures in 3D NAND flash memory is required to be more and more stacked, which makes the formation of three-dimensional memory It is becoming more and more difficult to etch the channel, and the cost of the process is getting more and more expensive, which seriously restricts the development of 3D NAND flash memory technology

Not only that, in the above process steps, the realization of silicon epitaxial growth, silicon and oxide deposition, ion implantation, etc. Difficult, and the more deposited layers, the easier it is to produce inter-film stress imbalance, resulting in wafer warping, which directly affects the accuracy of the photolithography process, and ultimately affects the reliability of the electrical performance of the memory unit

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