Method for making 3D NAND flash memory with a lot of stack layers, and 3D NAND flash memory

Abstract

The invention provides a method for making a 3D NAND flash memory with a lot of stack layers, and a 3D NAND flash memory. The method includes the following steps: providing a substrate wafer, whereinthe substrate wafer has an MOS device area and a first storage device area; providing a bonding wafer, wherein the bonding wafer has a metal connection wire area and a second storage device area; carrying out bonding connection: turning the bonding wafer to make the metal connection wire area correspond to the MOS device area and the second storage device area correspond to the first storage device area, and enabling the bonding wafer and the substrate wafer to be directly bonded with the help of Van der Waals force; and carrying out treatment after connection: thinning the substrate of the bonding wafer, making a metal interconnection layer, and forming metal connection wires between MOS devices and storage devices. The limit on the number of layers of an N/O stack structure in the existing process is overcome. A 3D NAND flash memory with a lot of stack layers is obtained. The storage capacity of the 3D NAND flash memory is improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a 3D NAND flash memory structure and a manufacturing method thereof, in particular to a manufacturing method of a high-stacked 3D NAND flash memory. Background technique [0002] With the development of planar flash memory, the production process of semiconductors has made great progress. However, in recent years, the development of planar flash memory has encountered various challenges: physical limits, existing development technology limits, and storage electron density limits. In this context, in order to solve the difficulties encountered in planar flash memory and to seek lower production costs per unit storage unit, various three-dimensional (3D) flash memory structures have emerged, such as 3D NOR (3D or not) flash memory and 3D NAND (3D NAND) flash memory. [0003] Wherein, in the 3D flash memory of the NOR structure, memory cells are arranged in parallel betw...

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Problems solved by technology

[0018] However, in the above process, in order to obtain a larger storage capacity per unit chip area, the number of O / N (Oxide / Nitride) stacked structures in 3D NAND flash memory is required to be more and more stacked, which makes the formation of three-dimensional memory It is becoming more and more difficult to etch the channel, and the cost of the process is getting more and more expensive, which seriously restricts the development of 3D NAND flash memory technology

Not only that, in the above process steps, the realization of silicon epitaxial growth, silicon and oxide deposition, ion implantation, etc. Difficult, and the more deposited layers, the easier it is to produce inter-film stress imbalance, resulting in wafer warping, which directly affects the accuracy of the photolithography process, and ultimately affects the reliability of the electrical performance of the memory unit

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