Fabrication method and gate structure of gate oxide layer of three-dimensional computer flash memory device

Abstract

The invention discloses a production method and a grid structure a gate oxide layer of a three-dimensional computer flash memory device. The production method includes the steps that a silicon substrate with a silicon nitride transitional layer on the surface is provided; a first silicon dioxide layer is formed on the surface of the silicon nitride transitional layer; a window running through thefirst silicon dioxide layer and the silicon nitride transitional layer and exposing the silicon substrate is developed; a monocrystalline silicon column is produced in the window, one end of which isin contact with silicon substrate while the other end beyond the first silicon dioxide layer; a second silicon dioxide layer is formed on that end, which deviates from the first silicon dioxide layer,of the monocrystalline silicon column; a default height clearance is arranged between the second and the first silicon nitride transitional layer; a grid oxide layer is produced through heat treatment, and the grid comprises a third silicon nitride transitional layer, which is located on the side of the monocrystalline silicon column, and a fourth silicon nitride transitional layer positioned onthe surface of the silicon substrate. With the technical solutions of the invention, grid oxide layers with uniform thickness are produced. Furthermore, pressure resistance and reliability of 3D NANDare improved.

Description

technical field [0001] The invention relates to the technical field of storage devices, and more specifically, relates to a method for manufacturing a gate oxide layer of a three-dimensional computer flash memory device and a gate structure. Background technique [0002] The fabrication method of the gate oxide layer of the existing three-dimensional computer flash memory device (3D NAND) is as follows: figure 1 and figure 2 as shown, Figure 1-Figure 2 It is a schematic flow chart of the manufacturing method of the gate oxide layer of the existing 3D NAND. [0003] First, through the semiconductor process technology to form such as figure 1 In the shown structure, at this time, there is a groove on the silicon substrate 11, and an N-type doped silicon layer 12 is deposited in the groove, and the surfaces on both sides of the N-type doped silicon layer are covered with a silicon dioxide layer 13. The silicon dioxide layer on the side has an opening, and a monocrystallin...

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Problems solved by technology

[0004] In the existing method for manufacturing the gate oxide layer of 3D NAND, since the surface of the silicon substrate 11 and the silicon dioxide layer 13 are pre-formed, the oxygen consumption on the side of the single crystal silicon column 11 will decrease during the subsequent heat treatment. Different from the oxygen consumption on the surface of the silicon substrate 11, the thickness of the silicon dioxide layer on the side of the monocrystalline silicon column 14 is different from the thickness of the silicon dioxide layer on the surface of the silicon substrate 11. In particular, between the monocrystalline silicon column 11 and the silicon The silicon dioxide layer formed in the area 17 where the substrate 11 is connected has a large thickness variation range, that is to say, in the existing manufacturing method, the thickness of the finally formed gate oxide layer will be uneven, and the withstand voltage performance will be poor. , affecting the reliability of 3D NAND

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