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Systems, devices and methods for temporarily loading instructions

A technology for loading instructions and instructions, applied in instruction analysis, memory system, concurrent instruction execution, etc., can solve problems such as register generation, pressure, difficult loading scheduling, etc.

Active Publication Date: 2021-07-20
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] When data is loaded from memory, needed for only one operation, and then discarded, this can create register pressure (especially when unrolling internal loops) and make it difficult to schedule loads and potentially hide "load-to-use" latencies
Thus, conventional systems suffer from register pressure and minimize data that is extremely transient in nature (only needs to exist for 1 cycle / 1 packet)

Method used

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  • Systems, devices and methods for temporarily loading instructions
  • Systems, devices and methods for temporarily loading instructions
  • Systems, devices and methods for temporarily loading instructions

Examples

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Embodiment Construction

[0021] Various aspects are disclosed in the following description and associated drawings to illustrate specific examples relevant to the present disclosure. Alternative examples will be apparent to those of skill in the art after reading the present disclosure, and can construct and practice alternative embodiments without departing from the scope or spirit of the present disclosure. Additionally, well-known elements will not be described in detail or may be omitted so as not to obscure the relevant details of the aspects and examples disclosed herein.

[0022] High-performance processors according to some examples of the present disclosure rely on superscalar and / or transient load instructions ( Such as Very Long Instruction Word (VLIW)) technology. These processors, such as ASIC 208, contain multiple functional units, execute sequential streams of instructions / input operands, are capable of fetching two or more instructions / input operands in clock cycles from memory, and c...

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Abstract

A transient load instruction for a processor may include transient or temporary load instructions that execute in parallel with multiple input operands. The temporary load instruction loads a memory value into a temporary location for use within the instruction packet. According to some examples, a VLIW-based microprocessor architecture may include a temporary cache for writing / reading temporary memory values ​​during a single VLIW packet cycle. The temporary cache is different from the normal register set which does not allow writing and then reading the value just written during the same VLIW packet cycle.

Description

technical field [0001] The present disclosure relates generally to memory load operations, and more specifically, to temporary load vector operations for very long instruction word (VLIW) based systems. Background technique [0002] In computing, an optimizing compiler is a compiler that attempts to minimize or maximize some property of an executable computer program. The most common requirement is to minimize the time it takes to execute a program; a less common requirement is to minimize the amount of memory used. The development of portable computers has created a market for minimizing the power consumed by programs. Compiler optimizations are generally implemented using a sequence of optimizing transformations, algorithms that take a program and transform it to produce a semantically equivalent output program that uses fewer resources. In the past, computer memory limitations were also a major factor limiting those optimizations that could be performed. Because of all...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/312G06F9/38
CPCG06F9/3824G06F9/3826G06F9/3853G06F9/383G06F9/30043Y02D10/00G06F1/10G06F9/30145
Inventor 艾瑞克·马胡林雅各布·帕维尔·戈拉布
Owner QUALCOMM INC