A time amplifier and a semiconductor memory

Abstract

The invention provides a time amplifier. At least one D trigger is embedded in the time amplifier. If a time point when a first time pulse reaches a first D trigger after delay of a preset time interval is different from a time point when a second time pulse reaches the first D trigger, a logic signal output by the first D trigger controls and adjusts the capacitance value of a second capacitor tobe less than the capacitance value of a first capacitor, so that the amplification gains of the time amplifier are reduced; or a logic signal output by the first D trigger controls and adjusts the capacitance value of the first capacitor to be less than the capacitance value of the second capacitor, so that the amplification gains of the time amplifier are increased. Thus, the gains of the time amplifier are adjustable. The invention also provides a semiconductor memory which has the above-mentioned technical effects.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a time amplifier and also to a semiconductor memory. Background technique [0002] Delay-locked loop (DLL, Delay-Locked Loop) is usually used in DDR3 / DDR4 dynamic random access memory. The delay-locked loop is used to automatically adjust the delay of one signal to make the phases of the two signals consistent (edge ​​alignment) . Specifically, when some digital signals need to be synchronized with the system clock, the delay-locked loop aligns the edges of the two clocks, and uses the adjusted clock as the control signal to generate a signal that is strictly synchronized with the system clock, and The synchronization does not change with changes in external conditions such as temperature and voltage, so it is widely used. [0003] In order to measure fine time intervals, a time-to-digital converter (TDC, Time-to-Digital converter) is embedded in the DLL. In recent years...

AI Technical Summary

Problems solved by technology

Among them, the SR latch-based time amplifier consists of two SR latches and a gate, and its gain is proportional to the additional capacitance set at the output of the SR latch, however, the SR latch-based time amplifier’s The main disadvantage is that the gain of time amplification cannot be adjusted according to actual needs, which leads to low accuracy of time interval measurement of DLL

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