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Semiconductor device

A technology of semiconductors and laminates, applied in semiconductor devices, electrical solid devices, electrical components, etc., can solve problems such as the deviation of the coupling ratio between the electrode layer and the channel, and the difficulty in forming storage holes

Active Publication Date: 2022-06-07
KIOXIA CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If the number of stacked electrode layers is increased, it is difficult to form storage holes with a uniform diameter in the stacking direction
The deviation of the diameter of the storage hole in the lamination direction will lead to the deviation of the coupling ratio between the electrode layer and the channel

Method used

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  • Semiconductor device
  • Semiconductor device
  • Semiconductor device

Examples

Experimental program
Comparison scheme
Effect test

no. 1 approach ＞

[0020]

[0021] figure 1 It is a schematic perspective view of the memory cell array of the semiconductor device of the first embodiment.

[0022] like figure 1 As shown, in the semiconductor device of the first embodiment, two directions parallel to the main surface 10 a of the substrate 10 and orthogonal to each other are referred to as the X direction and the Y direction, and the two directions relative to the X direction and the Y direction are The direction orthogonal to the direction is referred to as the Z direction. For example, the Z direction corresponds to the first direction, the X direction corresponds to the second direction, and the Y direction corresponds to the third direction.

[0023] The memory cell array 1 of the semiconductor device according to the first embodiment includes a laminate 100 including a plurality of electrode layers 41 , a plurality of columnar portions CL, and a plurality of separation portions ST. A plurality of electrode layers 41 a...

no. 2 approach ＞

[0077]

[0078] Figure 15 It is a schematic cross-sectional view of the memory cell array of the semiconductor device of the first embodiment. Figure 15 and relative to figure 1 Corresponds to a portion of the cross-section parallel to the X-Z plane. Figure 15 It is a schematic cross-sectional view taken out of the columnar portion CL and its surrounding portion.

[0079] like Figure 15 As shown, the memory cell array 2 of the semiconductor device of the first embodiment includes a laminate 10 , a columnar portion CL, a tunnel insulating film 31 , a plurality of charge storage portions 32 , and a plurality of blocking insulating films 33 .

[0080] The laminated body 100 includes a plurality of electrode layers 41 laminated on the substrate 10 along the Z direction through the insulator 40 . The layered body 100 includes a layered body 100 a including a part of the plurality of electrode layers 41 , and a layered body 100 b including another part of the plurality of ...

no. 3 approach ＞

[0112]

[0113] Figure 22 It is a schematic cross-sectional view of the memory cell array of the semiconductor device of the third embodiment. Figure 22 and relative to figure 1 Corresponds to a portion of the cross-section parallel to the X-Z plane. Figure 22 It is a schematic cross-sectional view taken out of the columnar portion CL and its surrounding portion.

[0114] like Figure 22 As shown, in the memory cell array 3 of the semiconductor device of the third embodiment, the blocking insulating film 33 is provided between the charge accumulation portion 32 and the electrode layer 41 and between the electrode layer 41 and the insulator 40 . The blocking insulating film 33 may not be provided between the charge storage portion 32 and the insulator 40 . Other configurations are the same as those of the semiconductor device of the first embodiment, for example. An insulator 70 is provided between the side wall of the separation portion ST and the source layer SL. T...

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PUM

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Abstract

A semiconductor device includes a laminate, a columnar portion, a first charge storage portion, and a second charge storage portion. The laminate includes a plurality of electrode layers, and the plurality of electrode layers are laminated along a first direction on a flat source line formed on the substrate or on a peripheral circuit formed on the substrate through an insulator . The plurality of electrode layers includes a first electrode layer and a second electrode layer disposed between the first electrode layer and the substrate. The columnar portion extends along the first direction within the laminated body. The first charge accumulation portion is provided between the first electrode layer and the columnar portion. The second charge accumulation portion is provided between the second electrode layer and the columnar portion. The first charge accumulation portion between the first electrode layer and the columnar portion has a first length along a second direction intersecting the first direction than the second electrode layer and the columnar portion. The second charge accumulating portion therebetween is long by a second length along the second direction.

Description

[0001] Related applications [0002] This application enjoys priority based on US Provisional Patent Application No. 62 / 376,740 (filing date: August 18, 2016). The present application includes the entire contents of the basic application by referring to the basic application. technical field [0003] Embodiments relate to a semiconductor device. Background technique [0004] A semiconductor memory device with a three-dimensional structure is proposed, in which a memory hole is formed in a laminate formed by laminating a plurality of electrodes, a columnar portion is provided in the memory hole, and between the plurality of electrode layers and the columnar portion, a memory hole is formed, respectively. A plurality of charge storage portions are provided along the layering direction of the layered body. In order to increase the capacity of the semiconductor memory device, it is desirable to increase the number of stacked electrode layers. If the number of stacked electrod...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/11556H01L27/11582H10B41/27H10B41/10H10B41/35H10B43/10H10B43/27H10B43/35
CPCH10B41/27H10B43/27H10B41/35H10B43/35H01L29/1037H01L29/40114H01L29/40117H10B41/10H10B43/10
Inventor 坂本渉
Owner KIOXIA CORP
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