Electronic packaging piece and manufacturing method thereof

Abstract

The invention provides an electronic packaging piece and a manufacturing method thereof. The electronic packaging piece comprises a coreless layer type circuit structure, an intermediary agent plate combined to the coreless layer type circuit structure, an electronic element arranged on the intermediary agent plate and a packaging layer wrapping the intermediary agent plate and the electronic element. According to the invention, by replacing the current packaging substrate with the coreless layer type circuit structure, it is facilitated that the electronic packaging piece is light, thin, short and small.

Description

technical field [0001] The present invention relates to a semiconductor packaging process, in particular to an electronic package and a manufacturing method thereof. Background technique [0002] With the vigorous development of the electronic industry, electronic products are gradually moving towards the trend of multi-functional and high-performance. Among them, the technologies applied in the field of chip packaging include: Chip Scale Package (CSP), Chip Direct Attach Package (Direct Chip Attached, DCA for short), Multi-Chip Module (MCM for short), or three-dimensional stacking of chips into a three-dimensional integrated circuit (3D IC) chip stacking technology, etc. [0003] figure 1 It is a schematic cross-sectional view of a conventional 3D IC chip stacked semiconductor package 1, which includes a silicon interposer (Through Silicon interposer, TSI for short) 10, and the silicon interposer 10 has opposite die placement sides 10a and transfer sides 10b, and a plural...

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Problems solved by technology

), the thickness D of the packaging substrate 17 is quite thick, about 1000 to 1500 μm (that is, 1mm to 1.5mm), which is not conducive to the miniaturization of products

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