ELECTRONIC PACKAGE AND MANUFACTURING METHOD thereof

Abstract

The invention discloses an electronic package and a manufacturing method thereof. A first shielding layer and a first electronic element are arranged on a first side of a bearing structure; accordingto the electronic packaging piece, the first shielding layer is arranged on the first side of the bearing structure, the second electronic element and the packaging layer wrapping the second electronic element are arranged on the second side of the bearing structure, and then the second shielding layer is arranged on the packaging layer, so that the first electronic element and the second electronic element do not influence each other due to the first shielding layer and the second shielding layer, and the reliability of the electronic packaging piece is improved.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to an electronic package and its manufacturing method. Background technique [0002] With the vigorous development of the electronic industry, electronic products are gradually moving towards multi-functional and high-performance trends. The technologies used in the field of chip packaging include Chip Scale Package (CSP for short), chip direct attach package (Direct Chip Attached, referred to as DCA) or multi-chip module packaging (Multi-Chip Module, referred to as MCM) and other flip-chip packaging modules, or the three-dimensional stacking of chips integrated into a three-dimensional integrated circuit (3D IC) chip stacking technology, etc. [0003] figure 1 A schematic cross-sectional view of a semiconductor package 1 for stacking 3D IC chips, which includes a through silicon interposer (TSI for short) 10, the silicon interposer 10 has an opposing die side 10a and an in...

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Problems solved by technology

[0006] However, it is known that in the manufacturing method of the semiconductor package 1, when the semiconductor chip 19 is a high-contact (I / O) function chip with a thin line width and line spacing, the silicon interposer 10 needs to be used as the semiconductor chip 19 and the semiconductor chip 19. The medium for signal transmission between the packaging substrates 17, because the silicon interposer 10 needs to have a certain aspect ratio control (that is, the aspect ratio of the conductive through-silicon via 100 is 100um / 10um), in order to produce a suitable silicon interposer 10 , so it often takes a lot of process time and the cost of chemicals, thereby increasing the difficulty of the process and the production cost

[0007] In addition, since the semiconductor chip 19 needs to be transferred to the circuit board through the silicon interposer 10 and the packaging substrate 17, and the packaging substrate 17 has a core layer containing glass fiber material, the thickness of the packaging substrate 17 is quite thick. Therefore, it is not conducive to the miniaturization of terminal electronic products

[0008] Also, when the semiconductor chip 19 is a high contact (I / O) functional chip with thin lines and wide line spacing, it is necessary to increase the area of ​​the layout of the silicon interposer 10 to connect multiple functional chips to the silicon interposer. 10 on the same side, resulting in an increase in the layout area of ​​the corresponding packaging substrate 17, which is not conducive to the miniaturization of terminal electronic products

[0009] In addition, even if the packaging substrate 17 of the core layer containing glass fiber material is avoided, and the chip with high contact (I / O) function is connected to the circuit layer, in order to achieve the purpose of reducing the overall thickness, some chips are processed by high frequency. Electromagnetic radiation will be generated after operation, and for the chips arranged on both sides of the circuit layer, there are only a few extremely thin circuit layers, this electromagnetic radiation will seriously affect the operation of other chips

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