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A configurable mailbox data buffer apparatus

A technology of data registers and mailboxes, applied in the fields of electrical digital data processing, instruments, digital computer components, etc.

Active Publication Date: 2018-03-16
MICROCHIP TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The solution must be fully configurable and efficient for silicon use

Method used

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  • A configurable mailbox data buffer apparatus
  • A configurable mailbox data buffer apparatus
  • A configurable mailbox data buffer apparatus

Examples

Experimental program
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Effect test

example 1

[0035] Example 1 shows an arrangement supporting 2 unidirectional buffers, a command word and a status word. A block of data flow control logic is assigned to the last accessed word of each of the buffers (note that the buffer length is arbitrary within the limit of the number of mailboxes supported). A data flow control logic block is also assigned to the command word. However, since access to the status word is controlled by software, no data flow control logic is required. Mailbox register MSIxMBXD9 is not used.

example 2

[0036] Example 2 shows an arrangement to support 2 bi-directional buffers and command words. A block of data flow control logic is assigned to the last accessed word of one of the buffers but not the other. This is because the application can ensure that only one processor will access a buffer after completing another buffer access. A data flow control logic block is also assigned to the command word.

[0037] Figure 5 exhibit Figure 5 The data is written to the channel in the upper half of the Figure 5 The data in the lower half of the read channel. The left side represents the master side and the right side represents the slave side. The actual mailbox 540 is accessed through a multiplexer 530 via a buffer register 510 or 520 for write operations and directly for read operations. Mailbox 540 is generally controlled by the master control core. However, the clock is provided by the master or the slave through the multiplexer 550 . Such as Figure 5 As shown in , th...

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Abstract

A single chip microcontroller has a master core and at least one slave core. The master core is clocked by a master system clock and the slave core is clocked by a slave system clock and wherein eachcore is associated with a plurality of peripheral devices to form a master microcontroller and a slave microcontroller, respectively. A communication interface is provided between the master microcontroller and the slave microcontroller, wherein the communication interface has a plurality of configurable directional data registers coupled with a flow control logic which is configurable to assign adirection to each of the plurality of configurable data registers.

Description

[0001] Related patent applications [0002] This application claims priority to US Provisional Patent Application No. 62 / 181,379, filed June 18, 2015, which is hereby incorporated by reference for all purposes. technical field [0003] The present invention relates to a multiprocessor embedded system, such as a microcontroller with multiple cores, and in particular, the present invention relates to a configurable mailbox data buffer device for such an embedded system. Background technique [0004] A multi-processor core microcontroller can be designed with completely separate cores, and each core can operate on a different system clock. Therefore, in order to provide the ability to communicate between the two cores, a specific communication interface is necessary. In particular, there is a need for means to quickly and reliably move small amounts of data across a clock boundary between two processors. The solution must be fully configurable and efficient for silicon use. ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/10G06F13/16G06F13/20G06F13/42G06F15/167
CPCG06F13/102G06F13/16G06F13/20G06F13/42G06F15/167
Inventor 迈克尔·卡瑟伍德戴维·米基布赖恩·克里斯
Owner MICROCHIP TECH INC