Variable cycle capacitor establishment asynchronous time sequence optimization circuit and optimization method

Abstract

The invention discloses a variable cycle capacitor establishment asynchronous time sequence optimization circuit and optimization method. The circuit structurally comprises a VINP differential signalinput end, a VINN differential signal input end, a VXP sampling hold circuit and a VXN sampling hold circuit, wherein the VXP sampling hold circuit is connected with an upper electrode plate of a positive N-bit binary capacitor array; the VXN sampling hold circuit is connected with an upper electrode plate of a negative N-bit binary capacitor array; the VXP sampling hold circuit and the VXN sampling hold circuit are connected with a two-stage dynamic comparator; a lower electrode plate of the positive N-bit binary capacitor array is connected with a CP array switching control unit; a lower electrode plate of the negative N-bit binary capacitor array is connected with a CN array switching control unit; and the output end of the two-stage dynamic comparator is connected with a variable cyclecontrol unit and an internal clock generation unit. By enabling the establishment time allocated to high-bit capacitors to be longer than the establishment time of low-bit capacitors, so that redundant waiting time of the low-bit capacitors is avoided.

Description

technical field [0001] The invention belongs to the field of integrated circuits, and relates to an asynchronous sequence optimization circuit and an optimization method for establishing variable-period capacitors. Background technique [0002] With the gradual shrinking of the process size and the improvement of the capacitor switching method, the current successive approximation analog-to-digital conversion circuit can not only achieve ultra-high-speed sampling of gigahertz at medium resolution, but also achieve ultra-high resolution at low sampling rate. Currently researching the hottest analog-to-digital conversion circuit structure. The performance limiting factors of high-speed successive-approximation analog-to-digital conversion circuits include the settling time of the binary sampling capacitor array, the latching speed of the comparator, and switching noise coupled from error sources (such as comparator offset and kickback capacitor mismatch). The settling time of...

AI Technical Summary

Problems solved by technology

If the same cycle is used, during the capacitor switching process, the low-level capacitors will be allocated extra settling time, which is a waste of the limited cycle

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