Constant migration rate method for extracting source/drain parasitic resistance in nanometer MOSFET

Abstract

The invention discloses a constant migration rate method for extracting source / drain parasitic resistance in a nanometer MOSFET. The method comprises the following steps of (1) in a nanometer CMOS device, measuring threshold voltages VT and linear region drain currents Ids under the condition of different source and drain voltages Vds; (2) according to measurement results, selecting a proper external bias voltage condition to ensure a channel migration rate to be constant under the condition; and (3) under the proper external bias voltage condition, according to a linear region drain current Ids model, calculating out a source / drain parasitic resistance R value. According to the method, the research for parameters of the nanometer CMOS device obtains further development, and the development of reliability detection of the nanometer CMOS device is facilitated. The extraction method is high in measurement precision and is widely applied to various MOS device structures such as CMOS, SONOS, FLASH and the like; and an experimental method is simple and easy in operation.

Description

technical field [0001] The invention relates to a research on source / drain parasitic resistance of a CMOS device, in particular to a method for extracting source / drain parasitic resistance in nanometer CMOS under the condition of constant mobility. Background technique [0002] The source / drain parasitic resistance reduces the gate voltage of the intrinsic circuit ((V gs ) and drain voltage (V ds ), which reduces the driving capability of the device and is an important parameter in CMOS devices. As the size of nano-CMOS devices continues to shrink, the channel resistance (R channel ) gradually decreases, and the source / drain parasitic resistance accounts for the total device resistance (R T =R+R channel ) The proportion is getting higher and higher, which has become the main factor restricting the development of nanometer CMOS devices. Therefore, how to accurately extract the source / drain parasitic resistance of a device is a very important topic in the research of smal...

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Problems solved by technology

Therefore, how to extract the source / drain parasitic resistance in small-scale nano-CMOS devices under the condition of constant channel mobility has become a new challenge.

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