FPGA-assisted high performance computing method and FPGA

Abstract

The invention discloses an FPGA-assisted high performance computing method and an FPGA. The method includes the following steps: enabling the FPGA to extract and parse original time data obtained froma time calibration source, and obtaining time calibration time information; performing computing to obtain a time calibration signal by using a preset time calibration algorithm according to the timecalibration time information and reference time information, and sending the time calibration signal to a time calibration device by using a data bus, wherein the reference time information is time information correspondingly generated according to a system clock. The scheme of the invention adopts a calibration source such as an IRIG-B code source as a clock source, and thus the network delay inan NTP software time calibration mode and the own time error of a standard NTP protocol can be avoided; and the clock calibration is performed by using a time calibration algorithm based on the characteristics of FPGA parallel processing, the time error caused by a serial operation mode can be avoided, the time accuracy of the clock calibration can be improved, and the requirements of industrialautomation schemes can be further met.

Description

technical field [0001] The invention relates to the field of industrial automation, in particular to an FPGA-assisted high-performance computing method and FPGA. Background technique [0002] With the development of science and technology in modern society, accurate time information is often required in the field of industrial automation to meet the needs of technology and related work. [0003] In the prior art, the NTP (Network Time Protocol, Network Time Protocol) software is generally used to correct the time, and the computer time is collected as the time source, and the clock is synchronized by the processor, and then sent to the user device. Theoretically, the existing time calibration method is effective, but the problem is that there will be a network delay when the computer sends the time information to the processor through the network; In this way, the processor is often not at the agreed time node when performing clock synchronization, but ahead or behind the t...

AI Technical Summary

Problems solved by technology

[0004] The object of the present invention is to provide a kind of FPGA auxiliary high-performance computing method and FPGA, to utilize the parallel processing characteristic of FPGA (Field-Programmable Gate Array, Field Programmable Gate Array) to carry out clock calibration, solve the problem that time error is too large, Improving the Time Accuracy of Clock Calibration

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