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Methods and apparatus for test insertion points

A technology of test data and input coupling, which is applied in the direction of measuring devices, measuring electricity, and measuring electrical variables, etc., can solve problems that affect test controllability and observability, digital analysis cannot test random access memory analog modules, etc.

Active Publication Date: 2018-05-22
TEXAS INSTR INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] However, the existence of modules containing random resistant faults that affect the controllability and observability of the test requires a full test challenge
Also, digital analysis cannot test random access memory (RAM) or analog blocks

Method used

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  • Methods and apparatus for test insertion points
  • Methods and apparatus for test insertion points
  • Methods and apparatus for test insertion points

Examples

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Embodiment Construction

[0018] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The drawings are not necessarily drawn to scale.

[0019] The term "coupled" may include connections to intermediate elements, and additional elements and connections may exist between any "coupled" elements.

[0020] figure 1 is a schematic diagram of a portion of circuit 100 . Circuit 100 includes upstream circuit elements 102 and 104 that provide inputs to non-testable module 106 . Untestable module 106 receives input 108 from circuit elements 102 and 104 and provides output 110 to the rest of the circuit represented by cloud 112 .

[0021] A non-testable module 106 does not operate in a manner amenable to scan testing, such as boundary scan testing. Example non-testable modules include: memory devices (such as RAM), analog modules, content addressable memory modules, and modules with hysteresis (where the current behavior depends on the ...

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PUM

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Abstract

The invention discloses methods and apparatus for test insertion points. Described examples include a method of providing K bits of test data (902) to a combinatorial circuit. The method further includes generating N bits of test data using the combinatorial circuit, where N is greater than K (904). The method further includes providing the N bits of test data (906) to a module under test.

Description

technical field [0001] The present application relates generally to circuit testing, and, in particular, to methods and circuits for inserting test data and watchpoints into modules. Background technique [0002] Beginning in 1985, several European and North American companies joined together to form the Joint Testing Action Group (JTAG). The stated task is to solve the problem of printed circuit board (PCB) manufacturing test, which becomes more difficult as integrated circuits (ICs) become smaller and more complex. The solution was eventually standardized as IEEE Standard 1149.1-1990 Test Access Port and Boundary Scan Architecture, the entire contents of which are hereby incorporated herein by reference. This industry standard specifies the test resources required to incorporate into an IC. [0003] Boundary scan is based on the concept of in-circuit test (ICT). In boundary-scan, the physical probes ("nails") placed in the mid-net in probe testing techniques are replace...

Claims

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Application Information

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IPC IPC(8): G01R31/3185
CPCG01R31/318597G01R31/318385G01R31/318547G01R31/31707G01R31/31723G01R31/3177
Inventor W·普拉迪普
Owner TEXAS INSTR INC