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Server architecture and running method

An operation method and server technology, applied in the field of servers, can solve the problems of unfavorable high integration of modules, inability to save BIOS storage chips in server architecture, high hardware cost, etc., and achieve the advantages of high integration, enhanced intelligence, and reduced hardware costs Effect

Active Publication Date: 2018-05-25
深圳中电长城信息安全系统有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The purpose of the embodiments of the present invention is to provide a server architecture, aiming to solve the problem that the existing server architecture cannot save the BIOS storage chip, the hardware cost is high, and it is not conducive to the high integration of modules

Method used

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  • Server architecture and running method

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Experimental program
Comparison scheme
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Embodiment 1

[0031] figure 1 It is a structural block diagram of the server architecture provided by the embodiment of the present invention, and is described in detail as follows:

[0032] A server architecture, including processor CPU, north bridge chip, south bridge chip, described server architecture also includes baseboard management controller BMC;

[0033] The CPU or the south bridge chip is connected with the SPI controller serial peripheral bus controller of the BMC through the LPC low pin number interface;

[0034] The storage medium of the BMC is divided into two areas, the first area stores the BMC code, and the second area stores the BIOS code.

[0035] figure 2 The connection diagram of the CPU or the south bridge chip and the BMC provided for the embodiment of the present invention is described in detail as follows:

[0036] Wherein, the south bridge chip is connected to the BMC through the LPC low pin number interface, the Pcie interface and the USB interface.

[0037]...

Embodiment 2

[0044] image 3 It is the implementation flowchart of the operating method provided by the embodiment of the present invention, and is described in detail as follows:

[0045] S301, the BMC marks the storage address of the BMC code stored in the first area as a ROMA address;

[0046] S302. Mark the storage address where the BIOS code is stored in the second area as a ROMB address;

[0047] Wherein, the ROMB address and the ROMA address are different addresses.

[0048] Figure 4 A sample diagram of dividing the ROMA address and the ROMB address of the BMC Flash ROM provided by the embodiment of the present invention.

[0049] The CPU or south bridge is connected to the SPI controller of the BMC through the LPC, and the firmware of the BMC is hung under the SPI controller.

[0050] In the Rom map, the storage address where the Firmware stores the BMC code is marked as a ROMA address, and the storage address where the Firmware stores the BIOS code is marked as a ROMA address...

Embodiment 3

[0053] Figure 5 It is an effect diagram of dividing the ROMA address and the ROMB address of the BMC Flash ROM provided by the embodiment of the present invention, and is described in detail as follows:

[0054] exist Figure 5 Among them, the 32MB BMC rom is divided into two areas, 0-24MB is the first area for storing BMCcode, and 24MB to 32MB is the second area for storing BIOS code area.

[0055] The setup process is as follows:

[0056] 1) Set up on the SPI controller of the BMC,

[0057] Divide the 32MB Flash Rom into two areas, ROMA: 00000000h~18000000h (24MB) and ROMB: 18000000h~1f000000h (8MB).

[0058] 2) According to AST2400 design instructions:

[0059] Control SCU2C: Misc.Control Register offset 2C position, Bit0, set to Enable.

[0060] The BMC code is placed at 00000000h~18000000h, and the execution of the BMC code remains unchanged. The BIOS code is placed between 18000000h and 1f000000h.

[0061] When the CPU accesses the SPI controller through LPC, the...

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Abstract

The invention is applicable to the server field and provides a server architecture and a running method. The server architecture comprises a central processing unit (CPU), a north bridge chip, a southbridge chip and a baseboard management controller (BMC), wherein the CPU or the south bridge chip is connected with a serial peripheral bus controller (SPI controller) of the BMC through an LPC interface with a small pin number; and a storage medium of the BMC is divided into two regions, a BMC code is stored in the first region, and a BIOS code is stored in the second region. The server architecture has the advantages that on the one hand, a BIOS storage chip is omitted, hardware cost is lowered, and high integration of the server architecture is benefited; and on the other hand, the BIOS code transmission mode is expanded, and the intelligent degree of the server architecture is increased.

Description

technical field [0001] The invention belongs to the field of servers, and in particular relates to a server architecture and an operation method. Background technique [0002] A server, also called a server, is a device that provides computing services. The composition of the server architecture includes processors, hard disks, memory, system buses, BIOS memory chips, etc., which are similar to general computer architectures, but due to the need to provide highly reliable services, processing power, stability, reliability, security, Scalability, manageability and other aspects of high requirements. [0003] However, the existing server architecture cannot omit the BIOS memory chip, the hardware cost is high and it is not conducive to the high integration of the module. The reason is that when the server architecture loads the BIOS, it needs to read the BIOS image file from the BIOS memory chip to boot the system. It can be seen that the BIOS memory chip cannot be saved. Si...

Claims

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Application Information

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IPC IPC(8): G06F1/18
CPCG06F1/183
Inventor 张伟进杨再松王飞舟石明林俊
Owner 深圳中电长城信息安全系统有限公司
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